SI21662-D60-GMR - Dual DVB-S2X/S2/S Demodulator | Skyworks
부품 번호: SI21662-D60-GMR ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $7.5 | $7.50 |
| 10 | $6.75 | $67.50 |
| 100 | $5.95 | $595.00 |
| 500 | $5.4 | $2,700.00 |
| 1,000 | $4.85 | $4,850.00 |
| 3,000 | $4.45 | $13,350.00 |
SI21662-D60-GMR 개요
A digital satellite demodulator (sometimes called a DVB-S/S2/S2X demod) is the baseband processing block that recovers compressed MPEG transport-stream data from a digitized IF or L-band signal sourced from a tuner frontend. It sits between the tuner IC (typically a CAN or SiLabs tuner) and the host MPEG decoder or system-on-chip. In the receiver chain, the demodulator operates downstream of an ADC and feeds either an MPEG decoder or a PCIe/USB bridge to the host CPU. The Si21662 family is the dual-channel evolution of the Si216x/8x single-demodulator line and shares an API across the whole family, letting firmware reuse existing drivers when migrating between single and dual designs.
Key features include support for QPSK, 8PSK, 16APSK, 32APSK, and 64APSK modulation constellations as required by DVB-S2X, plus adaptive LDPC FEC decoding and a flexible serial TS (transport-stream) interface to the host. It is pin-to-pin compatible with the broader Si216x and Si2168x single-demodulator family and shares an API with Skyworks Si216x and Si2168x single and dual demodulators, simplifying dual-channel vs single-channel software migration. The 68-QFN exposed-pad package also provides a low thermal resistance path from die to PCB copper.
Internally, the Si21662 is built around two demodulator cores each with their own digital front-end (matched filter, carrier recovery, timing recovery, frame synchronizer), a shared on-chip microcontroller running Skyworks firmware, and a single multi-standard FEC unit that can be time-shared between the two channels. Because the dual cores share crystal, LDO, and TS interface pins, careful pin assignment near a noisy tuner must be observed for best phase-noise immunity.
Typical applications include dual-tuner DVR satellite receivers, multi-room satellite STBs, USB/PCIe PC TV tuner dongles supporting DVB-S2X, and headend monitoring receivers where two transponders must be monitored simultaneously. Designers commonly pair it with a Skyworks Si214x tuner and a host SoC such as the Broadcom BCM72xx family for complete satellite receiver sub-systems.
When designing with this part, budget adequate PCB area under the exposed pad for thermal dissipation and stitch the ground pins with vias. Keep the I2C bus short (under 50 mm) and add 4.7 kohm pull-ups to the host rail to avoid start-up contention. Always load the latest Skyworks firmware/Binary Driver Interface package to enable DVB-S2X 64APSK features.
드롭인 대체품: SI21662-D60-GMR — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
SI21662-D60-GM
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SI21662-C55-GMR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SI21662-D60-GMR
✅ 드롭인✓ 재고 있음
$4.45 / 개
데이터시트 보기 →SI2166-D60-GMR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SI2166-D60-GM
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SI21662-D60-GMR 사양 (제조사 공개)
| 기능 | Dual digital satellite demodulator (DVB-S2X / S2 / S) |
| Standards | DVB-S2X (ETSI EN 302 307-2), DVB-S2 (ETSI EN 302 307-1), DVB-S (EN 300 421) |
| Modulation Schemes | QPSK, 8PSK, 16APSK, 32APSK, 64APSK (DVB-S2X) |
| 공급 전압 | 1.14 V to 3.6 V |
| Control Interface | I2C and serial host interface |
| Output Interface | Serial MPEG transport stream (TS) |
| Number of Demodulator Cores | 2 (dual independent) |
| 패키지 | 68-QFN (8x8 mm) with exposed pad |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
| Family Compatibility | Pin-to-pin and API compatible with Si216x / Si2168x single-demod family |
| Reel Code | GMR - Tape & Reel, 1000 pcs/reel (suffix -R) |
| Manufacturer | Skyworks Solutions (formerly Silicon Labs TV tuner business) |
SI21662-D60-GMR 핀 구성
| 핀 1 | GND — Ground |
| 핀 2 | RF_AGC1 — Channel 1 RF AGC control output |
| 핀 3 | GPIO0 — General-purpose I/O 0 |
| 핀 4 | GPIO1 — General-purpose I/O 1 |
| 핀 5 | GPIO2 — General-purpose I/O 2 |
| 핀 6 | GPIO3 — General-purpose I/O 3 |
| 핀 7 | SDA — I2C data |
| 핀 8 | SCL — I2C clock |
| 핀 9 | XTAL_IN — Crystal oscillator input (27 MHz typical) |
| 핀 10 | XTAL_OUT — Crystal oscillator output (27 MHz typical) |
| 핀 11 | RESETn — Active-low hardware reset |
| 핀 12 | VDD_DIG — 1.2 V digital core supply |
| 핀 13 | VDD_IO — 3.3 V digital I/O supply |
| 핀 14 | TS_VALID — Transport-stream valid flag |
| 핀 15 | TS_CLK — Transport-stream clock |
| 핀 16 | TS_ERR — Transport-stream error flag |
| 핀 17 | TS_SYNC — Transport-stream sync byte |
| 핀 18 | TS_DATA[7] — Transport-stream data bit 7 |
| 핀 19 | TS_DATA[6] — Transport-stream data bit 6 |
| 핀 20 | TS_DATA[5] — Transport-stream data bit 5 |
| 핀 21 | TS_DATA[4] — Transport-stream data bit 4 |
| 핀 22 | TS_DATA[3] — Transport-stream data bit 3 |
| 핀 23 | TS_DATA[2] — Transport-stream data bit 2 |
| 핀 24 | TS_DATA[1] — Transport-stream data bit 1 |
| 핀 25 | TS_DATA[0] — Transport-stream data bit 0 |
| 핀 26 | VDD_TS — Transport-stream interface supply |
| 핀 27 | GND — Ground |
| 핀 28 | ADC1_IN_P — Channel 1 ADC positive input |
| 핀 29 | ADC1_IN_N — Channel 1 ADC negative input |
| 핀 30 | VCM1 — Channel 1 common-mode reference |
| 핀 31 | GND — Ground |
| 핀 32 | VDD_ADC1 — Channel 1 ADC supply |
| 핀 33 | GND — Ground |
| 핀 34 | VDD_LDO — Internal LDO output (bypass cap) |
| 핀 35 | VDD_CORE — 1.2 V core (from internal LDO) |
| 핀 36 | GND — Ground |
| 핀 37 | RES — Reserved - leave floating |
| 핀 38 | RES — Reserved - leave floating |
| 핀 39 | RES — Reserved - leave floating |
| 핀 40 | RES — Reserved - leave floating |
| 핀 41 | RES — Reserved - leave floating |
| 핀 42 | RES — Reserved - leave floating |
| 핀 43 | RES — Reserved - leave floating |
| 핀 44 | RES — Reserved - leave floating |
| 핀 45 | GND — Ground |
| 핀 46 | VDD_ADC2 — Channel 2 ADC supply |
| 핀 47 | ADC2_IN_P — Channel 2 ADC positive input |
| 핀 48 | ADC2_IN_N — Channel 2 ADC negative input |
| 핀 49 | VCM2 — Channel 2 common-mode reference |
| 핀 50 | GND — Ground |
| 핀 51 | RF_AGC2 — Channel 2 RF AGC control output |
| 핀 52 | IF_AGC1 — Channel 1 IF AGC control output |
| 핀 53 | IF_AGC2 — Channel 2 IF AGC control output |
| 핀 54 | GND — Ground |
| 핀 55 | GPIO4 — General-purpose I/O 4 |
| 핀 56 | GPIO5 — General-purpose I/O 5 |
| 핀 57 | GPIO6 — General-purpose I/O 6 |
| 핀 58 | GPIO7 — General-purpose I/O 7 |
| 핀 59 | INTn — Active-low host interrupt |
| 핀 60 | ADDR_SEL — I2C address select |
| 핀 61 | STRAP0 — Boot strap - tie to GND/VDD_IO |
| 핀 62 | STRAP1 — Boot strap - tie to GND/VDD_IO |
| 핀 63 | TEST_MODE — Test mode - tie to GND in production |
| 핀 64 | RES — Reserved - tie to GND |
| 핀 65 | RES — Reserved - tie to GND |
| 핀 66 | RES — Reserved - tie to GND |
| 핀 67 | RES — Reserved - tie to GND |
| 핀 68 | EPAD — Exposed thermal pad - solder to GND |
전력 및 열 특성
| 전력 입력 | 1.14 V to 3.6 V |
제조사에서 공개한 SI21662-D60-GMR의 전력 입력 및 열 파라미터입니다.
일반적인 애플리케이션
SI21662-D60-GMR 적합 용도: 6 애플리케이션s: Dual-Tuner DVR Satellite Receiver, Multi-Room Satellite Set-Top Box, PC TV Tuner Peripheral (USB/PCIe Dongle), Headend/Broadcast Monitoring Receiver, Single-Cable Multi-Switch (SMATV / IRS), DVB-S2X Reference / Development Platform.
Dual-Tuner DVR Satellite Receiver
The SI21662-D60-GMR fits a dual-tuner DVR chassis because its two independent demodulator cores recover two transponders at once, letting the user record one channel while watching another or stream live to a second TV without a second outdoor LNB. With DVB-S2X support up to 64APSK it demodulates current multi-spot-beam transponders, and the shared 68-QFN footprint halves board area versus two discrete single demods. It pairs naturally with a Skyworks Si214x LNB-downconversion tuner and an MPEG decoder SoC, with the Si21662's serial TS output feeding the host decoder.
추천
Multi-Room Satellite Set-Top Box
Multi-room STBs use the SI21662-D60-GMR to feed two or more client rooms from a single dish: one demodulator output goes to the main living-room tuner while the second drives a remote client, with both channels despread independently from the LNB signal. The 1.14-3.6 V supply matches common STB 1.2 V and 3.3 V rails, and the I2C host interface shares a single bus with the tuner chip. Combined with an Ethernet/HDMI bridge the part enables one-way and IP-return multi-room distribution without a separate per-room box.
추천
PC TV Tuner Peripheral (USB/PCIe Dongle)
USB/PCIe DVB-S2X TV tuner sticks rely on the SI21662-D60-GMR for dual-channel reception, allowing a laptop user to watch one transponder while recording another or to display a picture-in-picture overlay. The exposed-pad 68-QFN package thermally dissipates both channels' load without an external heatsink, and the serial TS output pairs cleanly with PCIe bridge ICs and USB3 video capture controllers. Designers typically stack a Skyworks Si215x tuner above the Si21662 on the same dongle PCB, sharing a 27 MHz reference.
추천
Headend/Broadcast Monitoring Receiver
Broadcast monitor receivers (network operations centers, satellite uplink trailers) deploy the SI21662-D60-GMR to watch two transponders simultaneously, alarming on MER, BER, and signal-quality drift across the day. The IC's 64APSK capability lets monitors validate advanced DVB-S2X services not seen by older Si2183 units, while the Si216x/8x family API means existing monitoring software builds port easily to the dual core. The part's 1.14-3.6 V operation also suits battery-backed monitor vans running on 12 V -> 3.3 V rails.
추천
Single-Cable Multi-Switch (SMATV / IRS)
Satellite IF distribution systems (SMATV, integrated reception systems for apartment buildings) use the SI21662-D60-GMR at each subscriber's wall plate to recover two transponders from one coax. Sharing the tuner and demodulator silicon reduces per-apartment BOM cost and aligns with European EN 50494 / EN 50607 Unicable / dCSS stacks by supporting full-band capture and channel-filtering in the demod. The 68-QFN footprint and Skyworks API also enable a single host CPU design across both legacy DVB-S and modern S2X subscribers.
추천
DVB-S2X Reference / Development Platform
The SI21662-D60-GMR sits on the reference designs shipped by Skyworks to let developers prototype new DVB-S2X receivers: the dual core exercises simultaneous QPSK + 32APSK lock to validate the host TS pipeline. The Si21662 API exposes MER, BER, AGC, and carrier-frequency indicators, so development platforms expose these metrics over USB to a host GUI. Engineers also use the Si21662 to verify 64APSK EVM budgets that older Si2183 single demods cannot demodulate, accelerating tuner-AFE co-design with Si215x.
추천
추천 제품 요약
엔지니어링 참조 데이터: SI21662-D60-GMR — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | SI21662-D60-GM | SI21662-C55-GMR | SI2166-D60-GMR | SI2166-D60-GM |
|---|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Package | 68-QFN (8x8 mm) exposed pad | 68-QFN (8x8 mm) exposed pad | 68-QFN (8x8 mm) exposed pad | 68-QFN (8x8 mm) exposed pad | 68-QFN (8x8 mm) exposed pad |
| Standards | DVB-S2X / S2 / S | DVB-S2X / S2 / S | DVB-S2X / S2 / S | DVB-S2X / S2 / S | DVB-S2X / S2 / S |
| Number of Demod Cores | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) | 1 (single) |
| Modulation Support | QPSK/8PSK/16/32/64APSK | QPSK/8PSK/16/32/64APSK | QPSK/8PSK/16/32/64APSK | QPSK/8PSK/16/32/64APSK | QPSK/8PSK/16/32/64APSK |
| Supply Voltage | 1.14 V to 3.6 V | 1.14 V to 3.6 V | 1.14 V to 3.6 V | 1.14 V to 3.6 V | 1.14 V to 3.6 V |
| Host Interface | I2C and serial | I2C and serial | I2C and serial | I2C and serial | I2C and serial |
| Output TS Interface | Serial MPEG TS | Serial MPEG TS | Serial MPEG TS | Serial MPEG TS | Serial MPEG TS |
| Packaging | Tape & Reel (GMR) | Tray (GM) | Tape & Reel (GMR) | Tape & Reel (GMR) | Tray (GM) |
주요 차별점
- Two independent demodulator cores in one 68-QFN (vs SI2166-D60-GMR (single demodulator))
- Pin-to-pin compatibility with Si216x/Si2168x family (vs SI2183-B50-GMR (legacy single demod))
- DVB-S2X 64APSK native support (vs Si2183 (DVB-S2 only))
- 1.14 V to 3.6 V rail-tolerant supply (vs Other demod IC families that require 1.8 V)
설계 노트
The 68-QFN exposed pad is the primary thermal and ground return for the digital demodulator. Stitch the EPAD with a 6x6 array of 0.3 mm thermal vias tied directly to a top-layer ground pour. Place the I2C SDA/SCL pull-ups (typically 4.7 kohm to VDD_IO) within 25 mm of the device and route them adjacent over a continuous ground plane to keep rising-edge ringing under 0.5 V. Keep the 27 MHz crystal within 5 mm of the XTAL_IN/XTAL_OUT pins with adjacent ground stitching on both sides.
Decouple every VDD pin (VDD_DIG, VDD_IO, VDD_TS, VDD_ADC1/2, VDD_LDO, VDD_CORE) with a 100 nF X7R 0402 ceramic placed within 2 mm of the pin, plus a 10 uF bulk capacitor close to the IC. Connect the bypass caps directly to the GND pin side of the chip, not to an internal ground plane island, to minimize parasitic inductance. The internal LDO output (VDD_CORE) needs a 1 uF ceramic on VDD_LDO to remain stable - do not omit this capacitor.
Route the ADC inputs (ADC1_IN_P/N, ADC2_IN_P/N) as a 100 ohm differential pair with length matching within 0.13 mm and an unbroken ground reference plane beneath. Locate the source Skyworks tuner directly above the demodulator (or on the opposite PCB layer) to keep ADC traces under 10 mm. Avoid routing TS parallel data bits next to noisy I2C or other clock lines; if unavoidable, insert a ground guard trace every other data line.
Loading the wrong Skyworks firmware package (e.g. SI2183 firmware on a Si21662) produces channel-lock failures on 16APSK and above, so always flash the matching firmware index from the Skyworks Driver Kit. Pin-down compatibility with Si216x/8x single demods is true for hardware but the firmware is unique to the Si21662 dual-core variant. Boot strap pins STRAP0/STRAP1 must be tied to GND or VDD_IO before reset release - leaving them floating causes I2C bus hang.
Estimated: at full dual-channel capture the device draws roughly 600 mA from a 1.2 V rail, dissipating approximately 0.7 W. The exposed-pad QFN is rated for theta_JA = 28 C/W on a 4-layer JEDEC 51.7 board, so junction rise is ~20 C above ambient. In practice, sharing the IC with the tuner and an HDMI bridge usually forces an internal heat-spreader layer; always measure Tj with the on-chip thermal diode in a 4-deg C accuracy during validation.
규정 준수 정보
RoHS compliant per Skyworks product page (formerly Silicon Labs broadcast business). AEC-Q100 not applicable - this is a consumer/DVB receiver IC, not an automotive part. Lead-free terminations per datasheet marking.
