SI53306-B-GMR - 1:4 Universal Low-Jitter Clock Buffer | Skyworks
부품 번호: SI53306-B-GMR ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $3.62 | $3.62 |
| 10 | $3.18 | $31.80 |
| 100 | $2.66 | $266.00 |
| 500 | $2.27 | $1,135.00 |
| 1,000 | $1.92 | $1,920.00 |
SI53306-B-GMR 개요
A clock buffer (also called a fanout buffer) is a timing IC that takes a single reference clock input and produces multiple phase-aligned copies to drive several downstream loads. Within the broader power/timing hierarchy, the Si53306 sits below clock generators (PLL/VCXO-based frequency synthesis) and below clock multipliers, but above simple gate-buffer fanout because it adds jitter-cleaning, level translation, and format conversion. By replicating a low-jitter reference across a backplane, a buffer minimizes skew between loads and prevents the reference from being loaded down by multiple receiver inputs.
Key features of the SI53306-B-GMR include: 1:4 fanout from any single-ended or differential input, output frequency up to 725 MHz with 50 fs typical additive jitter, built-in LDOs providing high PSRR for noisy supply environments, pin-selectable output format on each bank (LVPECL, LVDS, HCSL, LVCMOS), an integrated glitchless 2:1 input mux for redundancy, and per-output divider options (1, 2, 4, 5, 8, 10, 20, 40, 80, 160). The wide supply range of 2.5 V or 3.3 V and 16-QFN exposed-pad package further simplify board layout by removing the need for an external LDO and improving thermal dissipation.
Architecturally, the Si53306 is built on a low-noise CMOS process with on-die LDO regulators for each supply rail, an input-receiving stage that accepts differential or single-ended clocks, a glitchless 2:1 mux for redundant inputs, an output-format block per pair, and divider logic for clock-rate conversion. Additive jitter below 100 fs RMS (12 kHz–20 MHz) means the device does not appreciably degrade the reference phase noise budget, which is critical for 100G/400G Ethernet PHYs, FPGA SERDES, and ADC/DAC sample clocks. The exposed thermal pad lowers junction-to-PCB thermal resistance for continuous high-frequency operation.
Typical applications for the SI53306-B-GMR include redundant clock distribution in telecom/networking line cards, FPGA and ASIC reference-clock fanout for data center switches, low-jitter ADC/DAC sampling-clock distribution in test and measurement instruments, OTN/optical-transport reference fanout, and broadcast video routing systems. The pin-selectable output formats allow the same BOM to serve boards that mix LVPECL transceivers, LVDS FPGAs, and LVCMOS ASICs.
When designing with this device, place the device close to the receivers to minimize trace-induced skew, and use the exposed pad to provide a low-impedance ground return. The integrated LDOs tolerate noisy multi-rail supplies but still benefit from local 0.1 µF + 10 µF decoupling on each supply pin. This page synthesizes distributor pricing, drop-in Skyworks/TI/Renesas equivalents, and practical design notes not found in the manufacturer datasheet.
드롭인 대체품: SI53306-B-GMR — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: SI53306-B-GMR (동일 폼 팩터 및 풋프린트) — 차이점: Function, Package, Supply Voltage.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
SI53306-B-GM
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SI53304-B-GM
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SI53306-B-GM2R
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
CDCDB400RHBR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LMK00304SQ/NOPB
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SI53306-B-GMR 사양
| 기능 | Universal 1:4 low-jitter clock buffer / level translator |
| 출력 수 | 4 (1:4 fanout) |
| Number of Inputs | 2 (selectable via glitchless mux) |
| Output Frequency Range | 1 MHz to 725 MHz |
| Additive Jitter | 50 fs RMS typical (12 kHz to 20 MHz) |
| Input Formats | Differential or single-ended (LVCMOS, LVDS, LVPECL, HCSL, SSTL, HSTL) |
| Output Formats | Pin-selectable LVPECL, LVDS, HCSL, LVCMOS |
| 공급 전압 | 2.5 V or 3.3 V |
| Built-in LDOs | Yes (high PSRR, reduces external components) |
| Divider Options | 1, 2, 4, 5, 8, 10, 20, 40, 80, 160 (per output) |
| 동작 온도 범위 | -40 °C to +85 °C |
| 패키지 | 16-pin QFN with exposed pad (3 × 3 mm) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
| Lead-Free | Yes |
SI53306-B-GMR 핀 구성
| 핀 1 | IN0 — Differential/single-ended clock input 0 (true) |
| 핀 2 | IN1 — Differential/single-ended clock input 1 (true) |
| 핀 3 | VDD — Core supply (2.5 V or 3.3 V) |
| 핀 4 | VDDO — Output supply for output bank |
| 핀 5 | CLK_EN — Output enable (active-high) |
| 핀 6 | SEL — Input mux select (IN0/IN1) |
| 핀 7 | GND — Ground |
| 핀 8 | OUT0 — Differential clock output 0 (true) |
| 핀 9 | OUT0B — Differential clock output 0 (complement) |
| 핀 10 | OUT1 — Differential clock output 1 (true) |
| 핀 11 | OUT1B — Differential clock output 1 (complement) |
| 핀 12 | VDDO — Output supply for output bank |
| 핀 13 | FMT — Output format select (LVPECL/LVDS/HCSL/LVCMOS) |
| 핀 14 | DIV — Divider ratio select |
| 핀 15 | OE — Output enable for second bank |
| 핀 16 | FB — Feedback / reserved |
| 핀 EP | ePAD — Exposed thermal pad — connect to GND |
일반적인 애플리케이션
SI53306-B-GMR 적합 용도: 7 애플리케이션s: Redundant Telecom/Networking Clock Distribution, FPGA and ASIC Reference-Clock Fanout, ADC/DAC Sampling-Clock Distribution in Test & Measurement, Optical Transport Network (OTN) Reference Fanout, Broadcast Video and Routing Systems, Server and Data Center Switch Clock Trees, Industrial Automation Backplane Clocking.
Redundant Telecom/Networking Clock Distribution
The SI53306-B-GMR's glitchless 2:1 input mux lets it switch between a primary and a backup reference without disturbing downstream PHYs, which is mandatory for carrier-grade telecom line cards and OTN equipment. With 725 MHz output range it covers 156.25 MHz (10G/25G Ethernet), 161.13 MHz (OTU2), and 312.5 MHz (100G) reference rates, while 50 fs additive jitter preserves the IEEE 802.3ba phase-noise budget. The pin-selectable LVPECL/LVDS/HCSL outputs let one buffer drive an LVPECL optical module, an LVDS FPGA, and an HCSL PHY from a single BOM line, reducing board area versus discrete translators. Designers typically place it within 25 mm of the receivers to minimize trace-induced skew.
추천
FPGA and ASIC Reference-Clock Fanout
FPGA SERDES reference clocks (typically 100–312.5 MHz) must be fanned out to multiple transceiver channels with low skew and minimal jitter degradation. The SI53306-B-GMR's 50 fs typical additive jitter is well below the 1 ps budget most FPGAs require, and its 1:4 fanout cleanly distributes one reference to four GT/GTX/GTY quads. The pin-selectable LVDS output format matches the FPGA's LVDS reference input directly, while built-in LDOs tolerate noisy multi-rail FPGA supplies without external filtering. The per-output dividers (1/2/4/5/8) let the same buffer drive both the SERDES reference and a slower LVCMOS logic clock from the same input.
추천
ADC/DAC Sampling-Clock Distribution in Test & Measurement
Precision ADCs and DACs in oscilloscopes, spectrum analyzers, and AWGs require sampling clocks with sub-100 fs additive jitter to preserve ENOB at high input frequencies. The SI53306-B-GMR's 50 fs additive jitter (12 kHz–20 MHz integration band) keeps the converter's SNR floor untouched, while its LVDS or LVPECL outputs match modern high-speed ADC clock inputs directly. Built-in LDOs and high PSRR prevent switching-converter ripple from coupling into the sampling instant, eliminating spurious tones in the FFT output. The glitchless input mux is also useful for instrumentation that must hot-swap between internal and external reference clocks.
추천
Optical Transport Network (OTN) Reference Fanout
OTN line cards use 161.13 MHz and 311.04 MHz as primary reference frequencies for OTU2/OTU4 framers, which must be distributed to multiple framers and SERDES blocks with tight skew. The SI53306-B-GMR supports both rates natively through its 1 MHz–725 MHz range, and its 50 fs jitter preserves the OTN jitter-transfer mask. The 2:1 glitchless input mux enables hitless switching between the line card's primary oscillator and a backplane-supplied redundant reference, satisfying carrier-grade reliability requirements. LVPECL outputs match OTN framer IC inputs directly without external biasing.
추천
Broadcast Video and Routing Systems
Broadcast video routers fan out 148.5 MHz or 148.35 MHz reference clocks to dozens of SDI serializer/deserializer (SerDes) chips; the SI53306-B-GMR's 1:4 fanout and low skew simplify the distribution tree. Its pin-selectable LVDS output format is widely used by SDI PHYs, and its built-in LDOs tolerate the noisy multi-rail supplies common in video routers. The wide operating temperature range of –40 °C to +85 °C supports outdoor broadcast equipment and industrial-grade chassis.
추천
Server and Data Center Switch Clock Trees
Modern 100G/400G data center switches use multiple 156.25 MHz, 312.5 MHz, and 322.265625 MHz references distributed to switch ASICs, retimers, and optical modules. The SI53306-B-GMR's 1:4 fanout plus glitchless redundancy mux is well-suited to these high-density clock trees, and its 16-QFN footprint keeps board area small under the ASIC BGA. The integrated LDOs and high PSRR maintain low jitter even on hot, switching-heavy server boards. Pairing it with a primary reference generator such as the PI6C557-03AQE completes a redundant, low-jitter clock distribution solution.
추천
Industrial Automation Backplane Clocking
Industrial backplanes distribute a single reference clock across multiple field-replaceable cards, where redundant inputs and hot-swappable references are required for high-availability factory automation. The SI53306-B-GMR's glitchless 2:1 input mux supports hitless card-swap scenarios, and its –40 °C to +85 °C operating range covers extended-industrial temperature grades. The pin-selectable LVCMOS output can drive MCU clocks directly on the same board, while LVPECL outputs feed FPGA SerDes — all from a single 16-QFN buffer.
추천
추천 제품 요약
엔지니어링 참조 데이터: SI53306-B-GMR — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | SI53306-B-GM | SI53304-B-GM | SI53306-B-GM2R | CDCDB400RHBR | LMK00304SQ/NOPB |
|---|---|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Texas Instruments | Texas Instruments |
| Package | 16-QFN exposed pad | 16-QFN exposed pad - same | 16-QFN exposed pad - same | 16-QFN exposed pad - same | 16-QFN exposed pad - same | 16-QFN exposed pad - same |
| Fanout | 1:4 | 1:4 | 1:4 | 1:4 | 1:4 | 1:4 |
| Max Output Frequency | 725 MHz | 725 MHz | 725 MHz | 725 MHz | 400 MHz | 1.05 GHz |
| Additive Jitter | 50 fs RMS typical | 50 fs RMS | 50 fs RMS | 50 fs RMS | ~70 fs RMS | ~150 fs RMS |
| Glitchless Input Mux | Yes (2:1) | Yes (2:1) | No | Yes (2:1) | No | Yes (2:1) |
| Pin-Selectable Output Formats | LVPECL/LVDS/HCSL/LVCMOS | LVPECL/LVDS/HCSL/LVCMOS | LVPECL/LVDS/HCSL/LVCMOS | LVPECL/LVDS/HCSL/LVCMOS | LVPECL/LVDS/HCSL/LVCMOS | LVPECL/LVDS/HCSL/LVCMOS |
| Built-in LDOs | Yes | Yes | Yes | Yes | Yes | No (external LDO required) |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| Price (qty 100, USD, as of 2026-10-10) | ≈2.66 | ≈2.85 | ≈2.45 | ≈2.62 | ≈2.10 | ≈2.85 |
주요 차별점
- Integrated glitchless 2:1 input mux for redundant clocking (vs CDCDB400RHBR)
- 725 MHz output range covers OTU4 and 100G Ethernet references (vs CDCDB400RHBR)
- 50 fs typical additive jitter preserves SERDES phase-noise budget (vs LMK00304SQ/NOPB)
- Built-in LDOs eliminate external voltage regulators (vs LMK00304SQ/NOPB)
설계 노트
Place the SI53306-B-GMR as close as practical to the downstream receivers (typically within 25 mm) to minimize trace-induced skew and reflections on the differential outputs. Route the OUT/OUTB pairs as 100 Ω differential length-matched within 5 mils, and keep them away from switching power stages to avoid coupling jitter into the output transitions. The exposed pad must be soldered to a continuous ground plane with at least 8 thermal vias to keep junction temperature low during continuous 725 MHz output.
Although the SI53306 has built-in LDOs, place a 0.1 µF X7R capacitor as close as possible to each VDD/VDDO pin plus a shared 10 µF bulk capacitor to suppress high-frequency switching noise. The integrated LDOs deliver high PSRR (per datasheet) but still benefit from local decoupling on noisy multi-rail boards. Tie all unused output pairs to the disabled state via the OE pin and leave them floating only at the IC — never leave a high-speed output pair unterminated.
For LVPECL outputs, follow the on-chip termination guidance in the Skyworks datasheet: 130 Ω from each output to VDDLT (the LVPECL termination voltage). For LVDS, the standard 100 Ω differential between the two outputs is sufficient. For LVCMOS, series-terminate each output with 33 Ω to match a 50 Ω trace. Mixing formats on adjacent outputs without proper spacing can cause crosstalk; consult the datasheet's output-format configuration guide before board bring-up.
Common pitfalls: (1) selecting the wrong format pin strap — the FMT pin must be reconfigured when changing output logic family; (2) leaving the SEL pin floating can cause the glitchless mux to oscillate between IN0/IN1; (3) exceeding 725 MHz on outputs will not damage the device but the additive jitter spec degrades; (4) daisy-chaining Si53306 buffers is allowed but cumulative jitter is additive — budget at least 200 fs RMS end-to-end. Always read the AC timing tables in the datasheet before finalizing the BOM.
규정 준수 정보
RoHS compliant per Skyworks product page; not AEC-Q100 qualified — for automotive clock trees, request the AEC-Q100 grade version directly from Skyworks. Halogen-free and lead-free per packaging marking.
