SI5366-C-GQR - 1.05GHz Jitter Attenuator Clock IC | Skyworks
부품 번호: SI5366-C-GQR ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $17.51 | $17.51 |
| 10 | $16.63 | $166.30 |
| 100 | $15.76 | $1,576.00 |
| 500 | $14.97 | $7,485.00 |
| 1,000 | $14.22 | $14,220.00 |
SI5366-C-GQR 개요
A jitter attenuator, also called a jitter cleaner or synchronizing clock multiplier, is a clock-timing IC built around a phase-locked loop (PLL) that takes a noisy or frequency-multiplexed reference clock and produces a low-jitter output locked to that reference. Within the clock management hierarchy, it sits between oscillators/clock generators and the high-speed serializers, FPGAs, and ASICs that consume the resulting clocks, making it a core building block of communication-system clock trees.
Key features include third-generation DSPLL technology for any-frequency clock synthesis, four selectable input references covering 8 kHz to 707.35 MHz, five independent outputs reaching 1049.76 MHz, and flexible output signaling with CML, CMOS, LVDS, and LVPECL levels. This combination lets one device serve both slow SONET synchronization references (such as 19.44 MHz or 8 kHz) and fast 622 MHz or 1 GHz serial-link clocks.
Architecturally, the digital PLL (DSPLL) replaces traditional analog loop-filter components with an on-chip digital loop filter, eliminating external RC tuning, improving repeatability, and enabling loop bandwidth selection without hardware changes. The C-grade device targets commercial operating ranges typical of communications equipment.
Typical applications include SONET OC-48/OC-192 line cards, Ethernet and Fibre Channel switch and router timing, and wireless baseband clock distribution where a jitter-cleaned reference drives data converters or SERDES blocks.
Design consideration: match the DSPLL loop bandwidth to the jitter transfer mask of your standard (e.g., SONET/SDH) and keep the 100-pin TQFP power pins well decoupled to preserve phase-noise performance.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet.
드롭인 대체품: SI5366-C-GQR — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: SI5366-C-GQR (동일 폼 팩터 및 풋프린트) — 차이점: Input Frequency Range, Output Frequency Range, Package, Maximum Output Frequency, Packaging.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
SI5366-C-GQ
✅ 드롭인✓ 재고 있음
$28.6 / 개
데이터시트 보기 →SI5366-B-GQ
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
가격 문의
데이터시트 보기 →SI5366-A-GQ
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
SI5366-C-GQR 사양
| 기능 | Clock Multiplier, Jitter Attenuator |
| PLL | Yes (DSPLL, third generation) |
| Number of Clock Inputs | 4 |
| Input Frequency Range | 8 kHz to 707.35 MHz |
| Number of Clock Outputs | 5 |
| Output Frequency Range | 8 kHz to 1050 MHz (max 1049.76 MHz) |
| Maximum Output Frequency | 1.05 GHz |
| Output Signal Types | CML, CMOS, LVDS, LVPECL |
| Input Signal Types | Clock |
| Typical Applications | SONET OC-48/OC-192, Ethernet, Fibre Channel |
| 동작 온도 | -40C to +85C |
| 패키지 | TQFP-100 (14x14 mm) |
| 실장 유형 | Surface Mount |
| Packaging | Tape & Reel (R suffix) |
| RoHS 상태 | Compliant |
SI5366-C-GQR tqfp-100 (14x14 mm) 핀 구성 가이드
SI5366-C-GQR(tqfp-100 (14x14 mm) 패키지)의 핀 구성입니다. 핀 번호, 기능, 연결 다이어그램은 제조사 데이터시트에 정의되어 있습니다. 정확한 풋프린트와 솔더링 지침은 해당 문서를 참조하십시오.
다음에 대한 상세 핀아웃 데이터 없음: SI5366-C-GQR.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
SI5366-C-GQR 적합 용도: 6 애플리케이션s: SONET OC-48/OC-192 Line Cards, Ethernet Switch and Router Timing, Fibre Channel SAN Switches, Wireless Base Station Clock Distribution, Test and Measurement Instrument Clocking, Data Center NIC and Storage Adapters.
SONET OC-48/OC-192 Line Cards
The SI5366-C-GQR is explicitly specified by Skyworks for SONET OC-48/OC-192 systems, where received line clocks carry excessive wander and jitter that must be removed before driving payload processing. Its four inputs accept the SONET synchronization hierarchy references from 8 kHz up to 707 MHz, while five outputs deliver cleaned 622.08 MHz or 19.44 MHz-class clocks in LVPECL or LVDS to framers and mappers. The DSPLL loop bandwidth is register-programmable, allowing designers to meet the ITU/ANSI jitter transfer masks defined for SONET equipment without external loop-filter redesign. Placing the SI5366 between the recovered line clock and the system clock tree provides a standards-compliant, single-chip jitter cleanup stage.
추천
Ethernet Switch and Router Timing
In Ethernet switches and routers, the SI5366-C-GQR cleans the backplane or synchronization Ethernet clock before distribution to MAC, PHY, and SERDES blocks. Inputs from 8 kHz to 707.35 MHz accept common references such as 25 MHz, 125 MHz, and 156.25 MHz, and five outputs up to 1049.76 MHz serve both low-speed management clocks and multi-gigabit SERDES references. Output format flexibility across CML, LVPECL, LVDS, and CMOS lets one device drive heterogeneous clock loads across a line card, reducing BOM count. Because jitter at the SERDES reference directly impacts eye margin, the DSPLL-based cleanup measurably improves link-budget headroom on long-reach or high-loss channels.
추천
Fibre Channel SAN Switches
Fibre Channel storage networks require strict transmit jitter compliance at 1.0625, 2.125, and 4.25 Gbaud rates, and the SI5366-C-GQR addresses this by attenuating reference jitter before it reaches the Fibre Channel serializer. The 1049.76 MHz maximum output matches the byte-rate reference used in 1x-class Fibre Channel links, and the four-input architecture allows failover between redundant timing sources with automatic reference switching. Skyworks lists Fibre Channel among the primary applications in the Si5366 datasheet, with DSPLL loop bandwidth programmable to the applicable MJSQ jitter budgets. Using LVPECL outputs minimizes added deterministic jitter into the SERDES clock input across backplane traces.
추천
Wireless Base Station Clock Distribution
Base station receive and transmit chains depend on low-jitter clocks for data converters and SERDES; the SI5366-C-GQR accepts a GPS-disciplined or network synchronization reference (for example 10 MHz or 19.44 MHz) and multiplies it to high-frequency converter clocks up to 1050 MHz. Its jitter-attenuation function removes reference spurs and phase noise accumulated through distribution amplifiers, protecting ADC and DAC SNR performance at the RF edge. Multiple inputs support holdover and reference-redundancy schemes common in macro-cell timing cards. LVDS outputs reduce crosstalk on densely routed boards, while CMOS outputs serve lower-frequency control and framing clocks from the same device.
추천
Test and Measurement Instrument Clocking
High-speed test instruments such as bit-error-rate testers, protocol analyzers, and oscilloscope timing boards need reconfigurable, low-jitter clocks across a wide frequency span. The SI5366-C-GQR covers 8 kHz to 1050 MHz with any-frequency synthesis through its DSPLL architecture, letting one instrument board sweep many standard and non-standard rates without swapping oscillators. Four inputs permit switching between an internal precision reference and the signal-under-test recovered clock for jitter-transfer measurements, a classic use of the Si5366 in lab equipment. Register-programmable loop bandwidth allows the instrument to characterize or comply with different jitter masks in firmware.
추천
Data Center NIC and Storage Adapters
Network interface cards and storage adapters aggregate PCIe and line-side serial links whose reference clocks originate from a single jittery source such as a spread-spectrum or backplane clock. The SI5366-C-GQR cleans this reference and delivers five independent outputs up to 1049.76 MHz, feeding both PCIe clock trees and Ethernet/Fibre Channel SERDES references from one device. CML and LVPECL output options drive 100-ohm differential backplane routes, while the CMOS outputs clock MAC and management logic. Its four-input design supports swapping between on-board oscillator and module-sourced timing, improving serviceability of hot-swappable adapters.
추천
추천 제품 요약
엔지니어링 참조 데이터: SI5366-C-GQR — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | SI5366-C-GQ | SI5366-B-GQ | SI5366-A-GQ |
|---|---|---|---|---|
| Package | TQFP-100 (14x14 mm) | TQFP-100 (14x14 mm) - same | TQFP-100 (14x14 mm) - same | TQFP-100 (14x14 mm) - same |
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Input Frequency Range | 8 kHz to 707.35 MHz | 8 kHz to 707.35 MHz | 8 kHz to 707.35 MHz | 8 kHz to 707.35 MHz |
| Maximum Output Frequency | 1.05 GHz | 1.05 GHz | 1.05 GHz | 1.05 GHz |
| Number of Inputs / Outputs | 4 in / 5 out | 4 in / 5 out | 4 in / 5 out | 4 in / 5 out |
| Output Levels | CML, CMOS, LVDS, LVPECL | CML, CMOS, LVDS, LVPECL | CML, CMOS, LVDS, LVPECL | CML, CMOS, LVDS, LVPECL |
| Packaging Format | Tape & Reel (R) | Tray | Tray | Tray |
주요 차별점
- Any-frequency DSPLL jitter attenuation (vs Generic PLL clock generators)
- Four redundant reference inputs (vs SI5366 single-design pin-count peers)
- Tray vs reel sourcing flexibility (vs SI5366-C-GQ)
설계 노트
Treat every output bank as a differential pair routeline: keep CML/LVPECL/LVDS traces as 100-ohm controlled-impedance pairs with matched lengths, and AC-couple CML outputs into 50-ohm systems where required. Jitter added by poor routing directly subtracts from the jitter margin the DSPLL just won back. Skyworks application guidance in the Si53xx family reference manual shows recommended termination networks per output type - follow these exactly rather than improvising resistor dividers, and avoid stubs on any differential pair.
The 100-pin TQFP has multiple VDDO banks so each output format can run at its own supply. Decouple each VDD/VDDO pin pair with 0.1 uF ceramics placed within 2 mm of the pin, plus bulk 10 uF per rail. Estimated: mixed LVPECL loads on all five outputs can draw appreciable current, so verify total supply current against the datasheet electrical tables for your exact output configuration before sizing regulators - do not rely on a single typical figure for all output formats.
The DSPLL loop bandwidth and the input/output frequency plan are configured through device registers, not pins - a design that powers up without correct register configuration will not clock. Use Skyworks ClockBuilder configuration tooling per the Si53xx family reference manual to generate the register map, verify the chosen loop bandwidth meets your jitter transfer mask (SONET/SDH masks are bandwidth-sensitive), and store the configuration in on-board EEPROM or a host MCU. Also confirm your C-grade selection matches your required operating temperature range before release.
규정 준수 정보
LCSC part listing C2666327 marks SI5366-C-GQR as ROHS. REACH/halogen/conflict-minerals declarations not present in provided data.
