SN65DP159RGZT - 6-Gbps HDMI 2.0 Retimer | Texas Instruments
부품 번호: SN65DP159RGZT ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $6.2 | $6.20 |
| 10 | $5.58 | $55.80 |
| 100 | $4.96 | $496.00 |
| 500 | $4.45 | $2,225.00 |
| 1,000 | $3.94 | $3,940.00 |
| 3,000 | $3.5 | $10,500.00 |
SN65DP159RGZT 개요
What is an HDMI retimer? An HDMI retimer (also called a signal conditioner or redriver-with-clock) is a mixed-signal interface IC that receives a degraded TMDS (Transition-Minimized Differential Signaling) stream, recovers its embedded clock, applies equalization and de-emphasis, and re-transmits a clean TMDS signal. Retimers sit in the signal chain hierarchy between TMDS redrivers (which only compensate channel loss) and full HDMI2.1 protocol converters (FRL). Compared with simple redrivers, retimers reduce both ISI jitter and random jitter, enabling HDMI 2.0b 4K60 8-bit signaling over longer cable runs.
Key features include adaptive and fixed receiver equalization for ISI compensation, output swing/pre-emphasis/transition-density drive control, integrated I2C control with pass-through EDID/HDCP/HPD logic, and DisplayPort dual-mode 1.1 cable adapter support. The retimer operates from a single 3.3V supply and exposes configurable registers via I2C for sink-side tuning of the recovered link.
Architecturally, the SNx5DP159 combines a CTLE (continuous-time linear equalizer) input stage, a CDR (clock-and-data recovery) PLL, and a TMDS driver with programmable pre-emphasis. The 48-pin RGZ package exposes all four TMDS lanes, the auxiliary/HEAC+/DDC pair, and full I2C-side configuration I/O. A smaller 40-pin RSB (WQFN) package version is also offered for space-constrained dongles.
Typical applications include HDMI 2.0b dongles and adapters, set-top boxes, notebook and docking stations, 4K TVs and projectors, gaming consoles, and DP++ to HDMI adapters. The chip is also used in HDMI splitter/selector boards that need to clean up jittery inputs from long upstream cables.
When designing with this device, place AC-coupling capacitors close to the TMDS input pins as required by HDMI, provide a clean 3.3V rail, and route the I2C lines with pull-ups. The HPD, DDC, and CEC paths must be level-shifted correctly when bridging between 3.3V and 5V HDMI logic.
This page synthesizes distributor pricing, drop-in package alternatives, and practical design notes for the SN65DP159RGZT HDMI retimer that are not consolidated on any single manufacturer or distributor page.
드롭인 대체품: SN65DP159RGZT — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
SN65DP159RGZR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SN65DP159RSBR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SN65DP159RSBT
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SN65DP159RGZT 사양
| 기능 | TMDS-to-HDMI level-shifter retimer |
| Supported Standards | DVI 1.0, HDMI 1.4a, HDMI 2.0b, DP++ 1.1 |
| Maximum Data Rate | 6 Gbps per lane |
| Number of TMDS Lanes | 4 (3 data + 1 clock) |
| 공급 전압 | 3.3 V |
| 동작 온도 | -40C to +85C |
| 패키지 | 48-VQFN (RGZ) 7x7 mm |
| Control Interface | I2C with pass-through EDID/HDCP/HPD |
| Receiver Equalization | Adaptive and fixed |
| Output Features | Programmable swing, pre-emphasis, transition-density control |
| AC Coupling | Required on TMDS inputs |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
| Lead-Free | Yes |
SN65DP159RGZT 핀 구성
| 핀 1 | TX2P — TMDS output lane 2 positive |
| 핀 2 | TX2N — TMDS output lane 2 negative |
| 핀 3 | TX1P — TMDS output lane 1 positive |
| 핀 4 | TX1N — TMDS output lane 1 negative |
| 핀 5 | TX0P — TMDS output lane 0 positive |
| 핀 6 | TX0N — TMDS output lane 0 negative |
| 핀 7 | TXCP — TMDS output clock positive |
| 핀 8 | TXCN — TMDS output clock negative |
| 핀 9 | VDD — 3.3V supply |
| 핀 10 | GND — Ground |
| 핀 11 | RX2P — TMDS input lane 2 positive (AC-coupled) |
| 핀 12 | RX2N — TMDS input lane 2 negative (AC-coupled) |
| 핀 13 | RX1P — TMDS input lane 1 positive (AC-coupled) |
| 핀 14 | RX1N — TMDS input lane 1 negative (AC-coupled) |
| 핀 15 | RX0P — TMDS input lane 0 positive (AC-coupled) |
| 핀 16 | RX0N — TMDS input lane 0 negative (AC-coupled) |
| 핀 17 | RXCP — TMDS input clock positive (AC-coupled) |
| 핀 18 | RXCN — TMDS input clock negative (AC-coupled) |
| 핀 19 | SDA — I2C data (pass-through) |
| 핀 20 | SCL — I2C clock (pass-through) |
| 핀 21 | HPD — Hot Plug Detect |
| 핀 22 | CAD — Cable Detect / Aux |
| 핀 23 | EQ_SEL0 — Equalization select 0 |
| 핀 24 | EQ_SEL1 — Equalization select 1 |
| 핀 25 | MODE0 — Operating mode select 0 |
| 핀 26 | MODE1 — Operating mode select 1 |
| 핀 27 | TX_TERM — TX termination control |
| 핀 28 | RX_TERM — RX termination control |
| 핀 29 | AUX_P — DisplayPort AUX channel positive |
| 핀 30 | AUX_N — DisplayPort AUX channel negative |
| 핀 31 | HEAC_P — HDMI Ethernet/Audio Return positive |
| 핀 32 | HEAC_N — HDMI Ethernet/Audio Return negative |
| 핀 33 | CEC — Consumer Electronics Control |
| 핀 34 | DDC_CLK — Display Data Channel clock |
| 핀 35 | DDC_DAT — Display Data Channel data |
| 핀 36 | VSADJ — Voltage swing adjust |
| 핀 37 | PRE_EMPH — Pre-emphasis control |
| 핀 38 | TD_CTL — Transition-density control |
| 핀 39 | TEST — Test mode (tie to GND in normal operation) |
| 핀 40 | RESET — Device reset (active low) |
| 핀 41 | VDD — 3.3V supply |
| 핀 42 | GND — Ground |
| 핀 43 | ADDR — I2C slave address select |
| 핀 44 | GPIO0 — General purpose I/O 0 |
| 핀 45 | GPIO1 — General purpose I/O 1 |
| 핀 46 | GPIO2 — General purpose I/O 2 |
| 핀 47 | NC — Not connected (per datasheet) |
| 핀 48 | NC — Not connected (per datasheet) |
일반적인 애플리케이션
SN65DP159RGZT 적합 용도: 7 애플리케이션s: DP++ to HDMI 2.0b Dongles, 4K UHD Television HDMI Inputs, Notebook and Docking Station HDMI Outputs, Set-Top Box and Streaming HDMI Outputs, Gaming Console HDMI Outputs, HDMI Splitter and Selector Boards, Projector and Home Theater AV Receivers.
DP++ to HDMI 2.0b Dongles
The SN65DP159RGZT is the canonical retimer for active DisplayPort dual-mode 1.1 to HDMI 2.0b dongles because it implements both the level-shifting logic and the TMDS clock-data recovery required for clean 6-Gbps signaling. Its adaptive receiver equalization compensates for the bandwidth-limited USB-C-to-HDMI cable assembly while the integrated CDR cleans up ISI jitter that would otherwise corrupt HDMI 2.0b 4K60 handshakes. Paired with a USB-C alternate-mode mux such as the TUSB1064 or HD3SS460, the SN65DP159RGZT completes a compact dongle BOM. Design tip: place the 0.1uF AC-coupling capacitors within 200 mil of the TMDS input pins per the datasheet layout guideline.
추천
4K UHD Television HDMI Inputs
Inside 4K UHD televisions, the SN65DP159RGZT serves as a front-end HDMI retimer on board inputs that must accept noisy TMDS streams from set-top boxes, game consoles, and HDMI cables up to 8 meters. The device's fixed-and-adaptive equalization recovers signal integrity at the HDMI 2.0b 6-Gbps rate, while the programmable output swing and pre-emphasis stabilize the link to the TV's HDMI 2.0b receiver SoC. The industrial -40C to +85C temperature range supports chassis-mount thermal conditions in slim TV enclosures. Pair with HDMI ESD protection such as the TPD8S009 for robust surge immunity.
추천
Notebook and Docking Station HDMI Outputs
Notebook PCs and Thunderbolt/USB-C docking stations route DisplayPort signals from the GPU through alternate-mode muxes to HDMI outputs, where the SN65DP159RGZT retimes the TMDS stream before the HDMI connector. The chip's I2C pass-through preserves EDID, HDCP, and HPD negotiation between the GPU and the HDMI sink without requiring a separate MCU. This makes the SN65DP159RGZT ideal for docking stations that must hot-plug into enterprise monitors at 4K60 over certified HDMI cables. Tip: keep the I2C lines isolated with pull-ups near the retimer to avoid contention with the GPU-side controller.
추천
Set-Top Box and Streaming HDMI Outputs
Set-top boxes and 4K streaming media players require a stable HDMI 2.0b output to deliver premium content with HDCP 2.2 protection. The SN65DP159RGZT provides the active retiming function needed to maintain HDMI 2.0b link integrity at the 6-Gbps TMDS rate, while its integrated level-shifting logic supports direct DP++ 1.1 dual-mode output from the host SoC. The chip's I2C pass-through allows HDCP repeater functionality, enabling downstream splitter/AVR topologies without an external repeater IC. The 48-pin RGZ 7x7 mm package suits compact set-top box PCB layouts with limited height clearance.
추천
Gaming Console HDMI Outputs
Gaming consoles outputting 4K60 HDR content over HDMI 2.0b benefit from the SN65DP159RGZT's CDR-based jitter cleaning, which tightens the TMDS eye margin before the cable and at the TV input. The device supports both fixed and adaptive receiver equalization so it can pre-compensate known cable losses in production firmware tuning, reducing per-console yield loss. Its -40C to +85C range covers the elevated thermal environment inside game-console chassis. Pair with the HDMI 2.0b ESD array TPD8S009 for comprehensive surge protection on the user-facing connector.
추천
HDMI Splitter and Selector Boards
HDMI splitters, matrix switches, and AV selector boards use the SN65DP159RGZT to clean up jittery upstream TMDS inputs before re-driving multiple HDMI outputs. The chip's adaptive receiver equalization recovers signal integrity from long cable runs feeding the splitter, while its programmable pre-emphasis maintains the output eye at each downstream HDMI 2.0b port. I2C control allows the splitter's MCU to tune the retimer per input channel for optimal performance with mixed cable lengths. The 48-VQFN RGZ 7x7 mm footprint simplifies multi-channel PCB layouts.
추천
Projector and Home Theater AV Receivers
AV receivers and home theater projectors with multiple HDMI 2.0b inputs rely on the SN65DP159RGZT to recover TMDS signals from long runs through walls and ceiling conduits, where high-frequency loss and ISI jitter accumulate. The chip's CDR-based retiming restores signal integrity before the HDMI 2.0b receiver, and its I2C pass-through preserves CEC, ARC, and EDID/HDCP handshake across the AV chain. Industrial temperature rating supports elevated thermal conditions in enclosed AV cabinets. Use the TPD8S009 ESD array on each HDMI connector for hot-plug surge protection.
추천
추천 제품 요약
엔지니어링 참조 데이터: SN65DP159RGZT — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | SN65DP159RGZR | SN65DP159RSBR | SN65DP159RSBT |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-VQFN (RGZ 7x7) | 48-VQFN (RGZ 7x7) - same | 48-VQFN (RGZ 7x7) - same | 48-VQFN (RGZ 7x7) - same |
| Maximum Data Rate | 6 Gbps | 6 Gbps | 6 Gbps | 6 Gbps |
| Supported Standards | DVI 1.0 / HDMI 1.4a / HDMI 2.0b / DP++ 1.1 | DVI 1.0 / HDMI 1.4a / HDMI 2.0b / DP++ 1.1 | DVI 1.0 / HDMI 1.4a / HDMI 2.0b / DP++ 1.1 | DVI 1.0 / HDMI 1.4a / HDMI 2.0b / DP++ 1.1 |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| I2C Pass-Through | Yes (EDID/HDCP/HPD) | Yes (EDID/HDCP/HPD) | Yes (EDID/HDCP/HPD) | Yes (EDID/HDCP/HPD) |
| Packaging Format | Tray (RGZT suffix) | Tape & Reel (RGZR suffix) | Tape & Reel (RSBR suffix) | Tray (RSBT suffix) |
주요 차별점
- Integrated DP++ 1.1 to HDMI 2.0b dual-mode support (vs SN65DP159RGZR)
- CDR-based retiming (vs simple redriver) (vs SN65DP159RSBR)
- Industrial -40C to +85C operating range (vs SN65DP159RSBT)
설계 노트
Place the AC-coupling capacitors as close as possible to the TMDS RX input pins (RX2P/N, RX1P/N, RX0P/N, RXCP/N) per the SNx5DP159 datasheet layout guideline. Use 0.1uF X7R ceramic capacitors with a short ground-return via fence. TMDS traces must be routed as 100-ohm differential pairs with length matching within 150 mil across each lane. The exposed thermal pad (EP) must be soldered to a continuous ground plane with multiple stitching vias for thermal dissipation.
The SN65DP159RGZT requires a clean 3.3V supply. Place 0.1uF and 10uF decoupling capacitors close to each VDD pin (pins 9 and 41), with a ferrite bead or pi-filter on the upstream 3.3V rail if shared with a noisy switching regulator. Avoid routing high-current switching node traces near the TMDS differential pairs, as crosstalk can degrade the HDMI 2.0b eye margin. Verify the supply ripple stays below 50 mVpp across all operating modes.
Do not omit the AC-coupling capacitors on the TMDS inputs - HDMI 2.0b requires AC coupling for inter-device compatibility. Do not tie the RESET pin high during normal operation; it must be driven high after power stable or left floating per the datasheet. The MODE0/MODE1 and EQ_SEL0/EQ_SEL1 strap pins must be configured for the correct operating mode at power-up; review the datasheet mode table to ensure proper HDMI 2.0b or DP++ 1.1 dongle behavior. The TEST pin must be tied to GND.
For 6-Gbps HDMI 2.0b signaling, keep TMDS trace lengths under 6 inches on the dongle board and under 12 inches on the host board. Use reference-plane stitching vias every quarter-wavelength along the differential pair to suppress return-path discontinuities. Maintain 100-ohm differential impedance with 85-ohm common-mode via FEXT isolation if crossing other high-speed lanes. Use the I2C registers to fine-tune pre-emphasis and swing per channel based on cable-length characterization data.
Place an HDMI ESD protection array such as the TPD8S009 at the HDMI connector with short ground-return traces to the chassis ground. The SN65DP159RGZT's CDR-based retiming reduces radiated emissions compared to passive redrivers, but the 6-Gbps output transitions still require spread-spectrum clocking or output edge-rate control to meet FCC Class B on consumer AV equipment. Common-mode chokes on the TMDS lines can further reduce radiated emissions if needed for AV receiver and TV applications.
규정 준수 정보
RoHS compliant per TI product page. Not AEC-Q100 qualified - the SN65DP159 family targets consumer AV and IT equipment rather than automotive applications. Lead-free VQFN RGZ package per JEDEC J-STD-020 MSL classification.
