THS1230CDWG4 - 12-Bit 30MSPS Low-Power ADC | Texas Instruments
부품 번호: THS1230CDWG4 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $8.42 | $8.42 |
| 10 | $7.55 | $75.50 |
| 100 | $6.4 | $640.00 |
| 500 | $5.5 | $2,750.00 |
| 1,000 | $4.85 | $4,850.00 |
THS1230CDWG4 개요
What is an ADC, and where does the THS1230 sit in the taxonomy? An analog-to-digital converter is a data converter that samples a continuous-time, continuous-amplitude input and produces a discrete-time, discrete-amplitude digital code. The hierarchy flows: ADC -> data converter -> mixed-signal IC -> semiconductor. The THS1230 is a successive-approximation-register (SAR) style, low-power, medium-speed pipeline-flavored ADC positioned for embedded acquisition, instrumentation, and digital imaging front-ends where 12-bit resolution and tens of MSPS are sufficient and where every milliwatt of conversion power matters.
Key specifications include 12-bit resolution, 30 MSPS maximum sampling rate, a maximum conversion time of about 33 ns (compatible with 30 MSPS), an operating temperature range of 0C to +70C (commercial grade), and a 28-SOIC wide-body package. Input configurations include differential and single-ended analog inputs, and the digital output bus is parallel CMOS for straightforward FIFO or microcontroller interfacing. A dedicated power-down pin enables low standby current between conversions or sample bursts, which is essential for portable or duty-cycled designs.
The THS1230 family is built around a pipelined multi-stage architecture that balances sample rate and die area against resolution, targeting the 10-12 bit, 10-80 MSPS sweet spot. Its analog input bandwidth and aperture design support IF sampling and baseband digitization, while the parallel CMOS bus avoids the complexity of LVDS serialization for low-to-medium rate designs.
Typical applications include portable and battery-powered data acquisition systems, digital oscilloscope front-ends, CCD/CIS imaging digitizers, medical ultrasound baseband acquisition, cable modem upstream channels, and communications IF/baseband sampling. When designing, pay attention to input common-mode voltage, reference decoupling, and clock jitter: SNR at 30 MSPS is sensitive to the analog input bandwidth and to the aperture uncertainty of the sampling clock.
드롭인 대체품: THS1230CDWG4 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: THS1230CDWG4 (동일 폼 팩터 및 풋프린트) — 차이점: Architecture, Operating Temperature, Package, Power-Down Mode.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
THS1230IDWG4
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
THS1230IDW
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
THS1230CDWRG4
✅ 드롭인✓ 재고 있음
$5.92 / 개
데이터시트 보기 →THS1230CDW
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
THS1231CDW
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
THS1230CDWG4 최대 정격 & 전기적 특성
| 분해능 | 12 bits |
| Sampling Rate (Max) | 30 MSPS |
| Number of Channels | 1 |
| Conversion Time (Max) | 0.033 us (approx. 33 ns) |
| Architecture | Pipelined, multi-stage |
| Data Interface | Parallel CMOS |
| Analog Input Configuration | Differential or single-ended |
| Nominal Supply Voltage | 3.3 V |
| Power-Down Feature | Yes (dedicated PD pin) |
| 동작 온도 범위 | 0C to +70C |
| 패키지 / 케이스 | 28-SOIC (DW), 0.295" / 7.50 mm width |
| 실장 유형 | Surface Mount |
| Lead-Free / RoHS | Yes (G4 green finish, RoHS compliant) |
THS1230CDWG4 핀 구성
| 핀 1 | AVCC — Analog supply voltage (3.3 V nominal) |
| 핀 2 | AGND — Analog ground |
| 핀 3 | AIN+ — Differential analog input, non-inverting |
| 핀 4 | AIN- — Differential analog input, inverting |
| 핀 5 | REFT — Top reference decoupling node |
| 핀 6 | REFB — Bottom reference decoupling node |
| 핀 7 | VREF — Voltage reference input/output |
| 핀 8 | AGND — Analog ground |
| 핀 9 | CLK — Sampling clock input |
| 핀 10 | PD — Power-down input (active high) |
| 핀 11 | OE — Output enable for parallel bus |
| 핀 12 | DVCC — Digital supply voltage |
| 핀 13 | DGND — Digital ground |
| 핀 14 | D0 — Data output LSB |
| 핀 15 | D1 — Data output |
| 핀 16 | D2 — Data output |
| 핀 17 | D3 — Data output |
| 핀 18 | D4 — Data output |
| 핀 19 | D5 — Data output |
| 핀 20 | D6 — Data output |
| 핀 21 | D7 — Data output |
| 핀 22 | D8 — Data output |
| 핀 23 | D9 — Data output |
| 핀 24 | D10 — Data output |
| 핀 25 | D11 — Data output MSB |
| 핀 26 | DRDY — Data ready / output clock |
| 핀 27 | DGND — Digital ground |
| 핀 28 | DVCC — Digital supply voltage |
일반적인 애플리케이션
THS1230CDWG4 적합 용도: 6 애플리케이션s: Portable Battery-Powered Data Acquisition, Digital Oscilloscope Front-End, CCD/CIS Imaging Digitizer, Medical Ultrasound Baseband Acquisition, Cable Modem / Communications IF Sampling, Industrial Test and Measurement.
Portable Battery-Powered Data Acquisition
The THS1230CDWG4 fits portable battery-powered data acquisition modules because it draws modest current at 30 MSPS and integrates a power-down pin that drops quiescent consumption to microamp range between conversion bursts. With 12-bit resolution and parallel CMOS output, it is accurate enough for sensor digitization in handheld multimeters, environmental loggers, and portable vibration analyzers. Designers place the IC after a low-noise input amplifier and reference, and read conversion data directly via the parallel bus into a low-power microcontroller for local buffering before wireless uplink. Compared with a switching-input ADC, the THS1230's single 3.3 V supply simplifies battery-rail design and avoids costly charge-pump or boost stages. The trade-off versus modern 16-bit ADCs is dynamic range, but for many field-portable sensor channels, 12 bits suffices.
추천
Digital Oscilloscope Front-End
The THS1230CDWG4 is widely used in the acquisition channel of entry-level and mid-range digital oscilloscopes where 12-bit resolution and 30 MSPS support baseband or low-bandwidth signal capture. Its single 3.3 V supply eases power-tree design, and the parallel CMOS bus streams conversion data directly into an FPGA-based timing and display engine without an LVDS deserializer. Front-end signal conditioning typically uses a programmable gain amplifier followed by the THS1230, with the clock provided by a low-jitter PLL synchronized to the timebase. Compared with a discrete AAF plus 8-bit ADC, the 12-bit resolution improves vertical accuracy and small-signal visibility. Engineers should pay attention to input bandwidth, aperture jitter, and reference decoupling to maintain SNR across the full scale.
추천
CCD/CIS Imaging Digitizer
Imaging front-ends for document scanners, industrial line-scan cameras, and digital copiers use the THS1230CDWG4 to digitize the analog output of a CCD or CIS sensor array. The 30 MSPS sample rate accommodates the pixel rate of moderate-resolution scanners, and the 12-bit code depth captures the dynamic range needed for grayscale shading and color separation (when paired with three ADCs and RGB filters). The parallel digital output interfaces directly to an image-processing ASIC or FPGA. Designers must route the analog input traces as 50-ohm controlled-impedance microstrips and isolate the analog and digital grounds to avoid pattern noise on the digitized image. The integrated power-down feature is useful for triggering sleep between scan lines to reduce average power.
추천
Medical Ultrasound Baseband Acquisition
The THS1230CDWG4 serves as the baseband digitizer in mid-tier portable ultrasound systems where 12-bit resolution and 30 MSPS are sufficient for envelope-detected RF channels. Each transducer channel typically uses a low-noise differential front-end followed by the THS1230, with conversion results fed into a beamforming FPGA or DSP. The single 3.3 V supply helps shrink the power budget for battery-driven carts, and the power-down pin enables quiescent gating between transmit pulses. Compared with newer 14-bit ultrasound ADCs, the THS1230 trades dynamic range for cost and availability. The wide-body SOIC package is easy to hand-solder during prototyping and to rework in production. Decoupling and clock-jitter hygiene are essential to maintain the SNR floor required for diagnostic image quality.
추천
Cable Modem / Communications IF Sampling
Set-top box return-path and cable modem upstream channels use the THS1230CDWG4 to digitize IF signals at moderate symbol rates. The 30 MSPS bandwidth supports oversampling of QPSK/QAM upstream channels, and the 12-bit dynamic range is adequate for the SNR required by DOCSIS return paths. The differential analog input accepts the output of an IF surface-acoustic-wave (SAW) filter plus a final IF amplifier. The parallel CMOS bus delivers samples directly into a QAM demodulation engine, typically implemented in a custom ASIC or FPGA. The single 3.3 V supply aligns with typical STB power rails, and the power-down pin enables idle savings between upstream allocations.
추천
Industrial Test and Measurement
The THS1230CDWG4 is well suited to bench-top instrumentation such as power analyzer modules, low-bandwidth spectrum analyzer IF strips, and protocol analyzers where clean 12-bit acquisition at 30 MSPS is sufficient. The commercial 0C to +70C range matches controlled-lab environments, and the wide-body SOIC eases hand rework during bring-up. Designers can synchronize multiple THS1230 devices to a common low-jitter clock for multi-channel acquisition (common in three-phase power analyzers), reading parallel data through a bank of FIFOs or an FPGA. The integrated power-down is convenient for trigger-armed acquisition where the converter idles between measurements. Compared with a high-speed oscilloscope ADC, the THS1230 sacrifices bandwidth for cost, but the 12-bit ENOB is acceptable for harmonic-distortion and efficiency measurements.
추천
추천 제품 요약
엔지니어링 참조 데이터: THS1230CDWG4 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | THS1230IDWG4 | THS1230IDW | THS1230CDWRG4 | THS1230CDW | THS1231CDW |
|---|---|---|---|---|---|---|
| Package | 28-SOIC (DW) | 28-SOIC (DW) - same | 28-SOIC (DW) - same | 28-SOIC (DW) - same | 28-SOIC (DW) - same | 28-SOIC (DW) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Sampling Rate (Max) | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS |
| Operating Temperature Range | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Supply Voltage (Nominal) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lead-Free / RoHS | Yes (G4 finish) | Yes (G4 finish) | Yes | Yes (G4 finish) | May be non-RoHS (no G4 marker) | Yes |
| Packaging Form | Tube (G4) | Tube (G4) | Tube | Tape & Reel (RG4) | Tube | Tube |
| Power-Down Pin | Yes | Yes | Yes | Yes | Yes | Yes |
주요 차별점
- Pin-compatible industrial-temp upgrade path (vs THS1230IDWG4)
- Tube and Tape & Reel variants share footprint (vs THS1230CDWRG4)
- Lead-free green finish with RoHS compliance (vs THS1230CDW (pre-RoHS))
- Integrated power-down pin for portable designs (vs Generic 12-bit 30 MSPS ADC without PD)
설계 노트
The THS1230CDWG4 operates from a single 3.3 V nominal supply and shares the rail across analog (AVCC) and digital (DVCC) domains. Place a 0.1 uF ceramic decoupling cap as close as possible to each AVCC and DVCC pin, with a 10 uF bulk tantalum or ceramic cap on each supply rail. A ferrite bead between AVCC and DVCC at the regulator output prevents digital switching noise from corrupting the analog reference. The PD (power-down) pin should be tied to logic low through a 100 kohm resistor if unused, and decoupled with a small cap to prevent false triggering.
Route the analog input traces as 50-ohm controlled-impedance microstrips and keep them short, symmetric, and away from digital output bus traces. Use a single continuous analog ground plane on the top layer under the analog input network, and stitch digital and analog grounds together at a single point near the THS1230's AGND pin. Place the reference bypass capacitors (REFT, REFB, VREF) immediately adjacent to their respective pins with short, fat traces. These layout measures are essential to preserve SNR and SFDR at 30 MSPS and to avoid pattern noise in imaging front-ends.
Estimated: at 30 MSPS, an aperture jitter of 5 ps rms limits SNR to roughly 68 dB on a 12-bit converter, so the sampling clock must come from a low-jitter source (clean crystal oscillator or PLL synthesizer, not a microcontroller GPIO). Drive CLK with a logic-level square wave through a series-termination resistor to match the trace impedance. Minimize the distance from the clock source to the CLK pin to keep jitter low. For applications demanding the full SNR, consider a dedicated clock buffer IC between the oscillator and the THS1230.
Avoid driving the THS1230's analog input outside the absolute maximum ratings (consult datasheet for AIN+ / AIN- absolute limits) or applying signals before AVCC is stable, which can cause latch-up. Do not leave the differential analog inputs floating - unused inputs should be biased to mid-supply through a resistor divider to avoid reference drift. Finally, ensure the parallel output bus does not toggle into a high-impedance bus conflict during power-up: control the OE pin from the host logic to a known state at startup.
규정 준수 정보
RoHS compliant per TI's THS1230 product page. The 'G4' suffix indicates the lead-free green finish. Not AEC-Q100 qualified - for automotive, evaluate other TI ADC families. REACH and conflict-minerals compliance per TI's material declaration.
