TPS7A5401RPST - 4A LDO Regulator, 1.1V VIN, 4.4µV Noise | Texas Instruments
부품 번호: TPS7A5401RPST ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $5.9 | $5.90 |
| 10 | $5.31 | $53.10 |
| 100 | $4.72 | $472.00 |
| 500 | $4.24 | $2,120.00 |
| 1,000 | $3.77 | $3,770.00 |
| 3,000 | $3.3 | $9,900.00 |
TPS7A5401RPST 개요
An LDO (low-dropout linear regulator) is a type of voltage regulator that maintains a regulated output even when its input voltage approaches the output voltage with only minimal headroom (the dropout). LDOs sit inside the broader hierarchy of linear regulators, which in turn belong to the voltage regulator family and the wider power-management IC category. Unlike switching DC-DC converters, LDOs dissipate the difference between VIN and VOUT as heat but add no switching noise, making them ideal for post-regulation of switching rails or for powering noise-sensitive analog circuitry.
Key specifications include 4.4 µVRMS output noise (10 Hz to 100 kHz), high PSRR of approximately 40 dB at 1 MHz, 4 A continuous output current, 175 mV maximum dropout at full load, and a sub-1.1 V minimum input voltage that allows direct operation from a 1.2 V or 1.8 V system rail without a preceding boost. Thermal resistance is engineered to support the 4 A load in a 2.2 x 2.5 mm outline when mounted with proper copper pours.
Architecturally, the TPS7A54 uses TI's advanced bipolar process with a precision bandgap reference, soft-start, current limit, and thermal shutdown. The exposed die-pad package enables direct heat extraction from the silicon into the PCB copper, critical at 4 A. Combined with its wide 0.8 V to 5.15 V adjustable output range, the device targets high-current, low-noise point-of-load applications including FPGA core/SerDes rails, ASIC supplies, and precision data-acquisition power trees.
Typical applications include powering noise-sensitive RF/SerDes blocks in networking line cards, FPGA and ASIC core rails in compact compute modules, high-current load-point regulation for test and measurement, and post-DCDC filtering for sensitive analog front ends in industrial and communications equipment.
When designing with this LDO, prioritize a low-impedance PCB copper pour under the exposed pad and place input/output ceramics as close to the pins as possible. For VIN-to-VOUT headroom above ~0.5 V at 4 A, derate continuously or use airflow; the 12-VQFN-HR package is small but dissipation scales linearly with drop.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet itself, plus pinout, comparison table, and selection guidance for engineers evaluating the TPS7A5401RPST for production use.
드롭인 대체품: TPS7A5401RPST — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: TPS7A5401RPST (동일 폼 팩터 및 풋프린트) — 차이점: Input Voltage Range, Output Voltage Range, Package, Topology.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
TPS7A5401RPSR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
TPS7A5401RPS
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
TPS7A5401QRGRRQ1
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
TLV1117LV33DCYR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
TPS7A4501RTER
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
TPS62841DLCR
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$0.65 / 개
데이터시트 보기 →TPS7A5401RPST 최대 정격 & 전기적 특성
| Manufacturer | Texas Instruments |
| Series | TPS7A54 |
| 출력 유형 | Adjustable (positive) |
| 출력 수 | 1 |
| 출력 전압 범위 | 0.8 V to 5.15 V |
| 최대 출력 전류 | 4 A |
| 입력 전압 범위 | 1.1 V to 6.5 V |
| Maximum Dropout Voltage | 175 mV at 4 A (max) |
| 출력 노이즈 | 4.4 uVRMS (10 Hz to 100 kHz) |
| PSRR | approximately 40 dB at 1 MHz |
| 동작 온도 범위 | -40C to +125C |
| 패키지 | 12-VQFN-HR (RPS, 2.2 mm x 2.5 mm) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
| 토폴로지 | Low-Dropout (LDO) Linear Regulator |
| Enable / Soft Start | Yes (per TI TPS7A54 family) |
TPS7A5401RPST 핀 구성
| 핀 1 | IN — Input voltage supply |
| 핀 2 | IN — Input voltage supply |
| 핀 3 | GND — Ground |
| 핀 4 | EN — Enable (active high, per TI TPS7A54 family) |
| 핀 5 | FB — Feedback input for adjustable output |
| 핀 6 | OUT — Regulated output voltage |
| 핀 7 | OUT — Regulated output voltage |
| 핀 8 | OUT — Regulated output voltage |
| 핀 9 | NC — Not connected (per datasheet) |
| 핀 10 | PG — Power-good indicator (open-drain) |
| 핀 11 | SS — Soft-start / noise-reduction capacitor |
| 핀 12 | BIAS — Bias supply input for low-VIN operation |
| 핀 EP | PAD — Exposed thermal pad - solder to PCB ground copper |
일반적인 애플리케이션
TPS7A5401RPST 적합 용도: 6 애플리케이션s: FPGA Core & SERDES Power, ASIC / SoC Point-of-Load, Test & Measurement Instrumentation, RF / Communications Line Cards, Industrial Automation Backplanes, High-Current Analog Front Ends.
FPGA Core & SERDES Power
The TPS7A5401RPST's 0.8 V to 5.15 V adjustable output covers the typical FPGA core (0.85 V to 1.2 V), SERDES analog (1.0 V to 1.5 V), and AUX (1.8 V to 3.3 V) supply rails in a single device. Its 4 A current and 1.1 V minimum VIN allow the LDO to be placed directly after a 1.2 V or 1.8 V intermediate bus, removing the need for a separate buck regulator per rail. The 4.4 µVRMS output noise is two to three orders of magnitude below typical FPGA PSRR requirements, eliminating the need for additional LC filtering on the analog SERDES rails, reducing BOM cost and board area in dense compute cards.
추천
ASIC / SoC Point-of-Load
High-performance ASICs and networking SoCs require point-of-load regulation with tight DC accuracy, low noise, and fast transient response at multi-amp currents. The TPS7A5401RPST delivers 4 A continuously with low dropout (175 mV max) and high PSRR across the audio band, making it suitable for post-regulation after a multi-phase buck converter where the residual switching ripple must be removed before reaching noise-sensitive clock or SerDes domains. The 12-VQFN-HR (2.2 x 2.5 mm) footprint allows dense placement right at the load, minimizing PCB parasitic losses on high-current traces and simplifying thermal design with direct copper-pour heat extraction.
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Test & Measurement Instrumentation
Precision test instruments such as AWGs, digitizers, and signal-source analyzers require analog rails whose noise floor sets the overall instrument accuracy. The TPS7A5401RPST provides 4.4 µVRMS noise over 10 Hz to 100 kHz with 4 A of headroom for powering ADC drivers, reference buffers, and FPGA fabric in a single regulator. Compared with discrete low-noise references plus op-amp buffers, this integrated LDO reduces board space and design time while still meeting the noise floor demanded by 16-bit and 18-bit instrumentation-grade ADCs, where each LSB at 5 V full scale equals only 38 µV.
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RF / Communications Line Cards
In base-station and small-cell RF line cards, transceiver noise directly determines EVM and ACLR performance; the TPS7A5401RPST can power the LNA, mixer, and LO buffer stages from a clean 1.2 V or 1.8 V rail without adding measurable phase noise. The wide 6.5 V input ceiling allows the same part to feed 3.3 V and 5 V analog sections of a transceiver chain. The 12-VQFN-HR package places heatsinking directly into the inner copper layers, which is essential for line cards that must operate at 85C ambient inside sealed enclosures.
추천
Industrial Automation Backplanes
Industrial control backplanes often run on 24 V nominal with intermediate 5 V and 3.3 V rails fed through isolation barriers. The TPS7A5401RPST can be placed downstream of an isolated 5 V or 3.3 V DC-DC module to provide clean post-regulation for microcontroller cores, sensor signal chains, and communication PHYs without introducing switching noise. The 175 mV maximum dropout at 4 A means the LDO can sustain full load even when the input bus sags to 4.9 V during input transients typical of industrial environments, preventing brown-out resets in safety-critical PLC subsystems.
추천
High-Current Analog Front Ends
Multi-channel data-acquisition front ends require low-noise power for op-amps, instrumentation amplifiers, and ADC drivers while drawing hundreds of milliamps per channel. The TPS7A5401RPST's 4 A capability and 4.4 µVRMS noise are well-matched to 8 to 16-channel AFEs, where a single LDO can supply the entire signal-chain block and eliminate channel-to-channel gain mismatch caused by unequal supply impedance. The exposed die-pad package and 2.2 x 2.5 mm outline minimize thermal gradients across the AFE, which would otherwise introduce offset drift in sensitive measurement circuits operating across -40C to +125C.
추천
추천 제품 요약
엔지니어링 참조 데이터: TPS7A5401RPST — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | TPS7A5401RPSR | TPS7A5401RPS | TPS7A5401QRGRRQ1 | TLV1117LV33DCYR | TPS62841DLCR |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 12-VQFN-HR (RPS, 2.2x2.5 mm) | 12-VQFN-HR (RPS, 2.2x2.5 mm) - same | 12-VQFN-HR (RPS, 2.2x2.5 mm) - same | RGR (QFN, automotive) | SOT-223 | VQFN-HR |
| Output Voltage Range | 0.8 V to 5.15 V (adj.) | 0.8 V to 5.15 V (adj.) | 0.8 V to 5.15 V (adj.) | 0.8 V to 5.15 V (adj.) | 3.3 V (fixed) | buck, not LDO |
| Automotive Qualification | No (industrial) | No (industrial) | No (industrial) | Yes (AEC-Q100, Q1 suffix) | No | No |
주요 차별점
- 4 A output current from a 12-VQFN-HR (2.2 x 2.5 mm) footprint (vs TLV1117LV33DCYR (1 A, SOT-223))
- 4.4 uVRMS ultra-low noise floor (vs Generic 1 A LDO regulators (60+ uVRMS typical))
- 1.1 V minimum input voltage (vs Standard LDOs with 2.7 V or higher minimum VIN)
- 175 mV max dropout at 4 A (vs TPS7A45 family (1.5 A, 250 mV dropout))
설계 노트
Estimated: at VIN=5 V, VOUT=3.3 V, and full 4 A load, power dissipation is (5-3.3)*4 = 6.8 W. The 12-VQFN-HR (RPS) package with a 1-oz 4-layer PCB copper pour can typically dissipate 2-3 W before derating curves force output current reduction. For full 4 A operation at any VIN-VOUT differential above ~0.5 V, plan for 4-layer PCB with 2-oz copper on inner layers, or forced-air cooling, or accept thermal derating.
Place input and output ceramic capacitors (TI recommends 10 µF X7R minimum on input and output) within 1-2 mm of the IN and OUT pins. Use wide copper pours on both top and inner layers under the exposed pad (EP) and stitch with thermal vias (0.3 mm diameter, 1 mm pitch) to inner ground planes. Keep high-current traces on the top and bottom layers to minimize parasitic inductance that would degrade load-transient response.
The exposed die pad (EP) MUST be soldered to the PCB copper for both thermal and electrical performance. Use a via farm of at least 9 thermal vias under the EP, connecting to inner ground copper. Avoid running signal traces directly under the EP - this creates parasitic coupling and noise injection into noise-sensitive analog domains. Place the FB resistor divider close to the FB pin with the lower resistor tied to a quiet ground (the same ground as the EP).
Do not operate above the absolute maximum VIN of 6.5 V (per TI datasheet); transients above this can permanently damage the device. The BIAS pin (if used) must be at least 1.6 V above VOUT for the internal charge pump to function correctly - tying BIAS to VOUT is acceptable when VOUT is at least 1.6 V. Avoid using ceramic output capacitors below 4.7 µF, which can cause instability due to insufficient phase margin. Always verify stability with a load-step and Bode plot during prototype validation.
규정 준수 정보
Standard TPS7A5401RPST is industrial-grade. For AEC-Q100 automotive applications use the TPS7A5401QRGRRQ1 (Q1 suffix) variant - different package outline (RGR). RoHS and REACH compliance per TI product page. Halogen-free per TI packaging markings.
