TXB0104YZTR - 4-Bit Auto-Direction Level Translator | TI
부품 번호: TXB0104YZTR ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $0.62 | $0.62 |
| 10 | $0.55 | $5.50 |
| 100 | $0.42 | $42.00 |
| 500 | $0.35 | $175.00 |
| 1,000 | $0.29 | $290.00 |
TXB0104YZTR 개요
A voltage-level translator is a logic-interface device that allows integrated circuits operating at different supply voltages - for example a 1.8V microcontroller and a 5V sensor - to exchange digital signals reliably. Within the power-management and interface hierarchy, level translators sit between logic families such as CMOS and TTL, complementing buffers, bus switches, and transceivers in the broader signal-chain category. Without translation, low-voltage logic can be damaged by higher-voltage inputs or fail to meet higher-voltage logic thresholds.
Key features of the TXB0104 include its two separate configurable power-supply rails (VCCA tracks the A port, VCCB tracks the B port, with VCCA <= VCCB), auto-direction sensing that eliminates direction-control pins, a maximum propagation delay of 13.7 ns, and 4 kV (HBM) class robustness supplemented by +/-15 kV IEC ESD protection on the I/O lines. The TXB architecture uses a mixed-charge pump output driver that pushes data in either direction without OE-based handshaking.
Technically, the device derives its drive from a 4 kOhm output stage optimized for lightly loaded, point-to-point CMOS links; it is not a bus-holder for heavily capacitive or high-fanout loads. The 0.5 mm ball pitch and wafer-scale DSBGA packaging minimize board area, making it attractive for dense portable designs. The output enable (OE) pin tri-states all channels for power-aware sequencing.
Typical applications include translating I2C-adjacent push-pull buses, SPI and UART links between 1.8V MCUs and 3.3V or 5V peripherals, SD-card interfaces, and general-purpose GPIO bridging in industrial and consumer systems.
A key design consideration: avoid capacitive loads above roughly 30 pF and pull-up/pull-down resistors below about 25 kOhm, because the auto-direction scheme relies on one side driving the line; contested drivers cause bus contention.
This page synthesizes distributor pricing, verified specifications, and practical design guidance for the TXB0104YZTR beyond what any single datasheet page provides.
드롭인 대체품: TXB0104YZTR — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
이 제품에는 사용 가능한 드롭인 대체품이 없습니다.
대체품 요청TXB0104YZTR 최대 정격 & 전기적 특성
| 기능 | 4-Bit Bidirectional Voltage-Level Translator |
| Direction Control | Automatic direction sensing |
| A Port Supply (VCCA) | 1.2 V to 3.6 V |
| B Port Supply (VCCB) | 1.65 V to 5.5 V |
| Supply Constraint | VCCA <= VCCB |
| Number of Channels | 4 |
| Maximum Data Rate | 100 Mbps |
| Maximum Propagation Delay | 13.7 ns |
| ESD Protection (IEC) | +/-15 kV |
| 패키지 | 12-DSBGA (YZT), 1.9 mm x 1.4 mm |
| Terminal Pitch | 0.5 mm |
| 동작 온도 | -40C to +85C |
| 실장 유형 | Surface Mount |
| Output Polarity | TRUE |
| Supply Voltage Max (VCCA) | 3.6 V |
| RoHS 상태 | Compliant (per TI product listing) |
TXB0104YZTR 12-dsbga (yzt), 1.9 mm x 1.4 mm 핀 구성 가이드
TXB0104YZTR(12-dsbga (yzt), 1.9 mm x 1.4 mm 패키지)의 핀 구성입니다. 이 디지털 IC에는 GPIO, 통신 인터페이스(UART, SPI, I2C), 전원 핀이 포함되어 있습니다. 대체 핀 기능과 구성 옵션은 제조사 데이터시트를 참조하십시오. 임베디드 시스템 설계와 PCB 레이아웃에 필수적입니다.
다음에 대한 상세 핀아웃 데이터 없음: TXB0104YZTR.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
TXB0104YZTR 적합 용도: 6 애플리케이션s: MCU-to-Peripheral SPI/UART Translation, SD Card Interface Level Shifting, Portable and Wearable Electronics, Industrial Control and PLC I/O, Consumer Display and Camera Modules, General-Purpose GPIO Voltage Bridging.
MCU-to-Peripheral SPI/UART Translation
The TXB0104YZTR bridges a 1.8V or 2.5V microcontroller's SPI or UART pins to 3.3V or 5V peripherals. Its auto direction sensing handles the bidirectional MOSI/MISO and RX/TX lines without a DIR control pin, and the 13.7 ns maximum propagation delay preserves SPI timing margins at clock rates into the tens of MHz. Because the four channels match a typical SPI cluster (SCLK, MOSI, MISO, CS), a single DSBGA-12 device implements the whole translation in 1.9 mm x 1.4 mm. Designers should keep traces short and load capacitance below roughly 30 pF so the ~4 kOhm TXB drivers meet edge rates; the auto-direction scheme requires the peripheral side to drive MISO rather than tri-state it.
추천
SD Card Interface Level Shifting
SD/SDIO cards initially power up in 3.3V mode, while many modern host SoCs and eMMC controllers run at 1.8V signaling; the TXB0104YZTR translates CMD and DAT lines during this negotiation. Its 100 Mbps capability comfortably exceeds the ~25 MHz default-speed SD clock, and the +/-15 kV IEC ESD rating on I/O adds robustness at the card slot, a user-accessible interface. The auto-direction feature suits the bidirectional CMD line without host firmware involvement. TI's datasheet application section explicitly addresses this use case; designers should ensure the translator is powered from both VCCA (host) and VCCB (card) rails that respect the VCCA <= VCCB constraint, and avoid pull-downs below about 25 kOhm that contest the TXB drivers.
추천
Portable and Wearable Electronics
In battery-powered wearables and phones, board area is the scarcest resource; the TXB0104YZTR's 1.9 mm x 1.4 mm DSBGA-12 with 0.5 mm pitch occupies a fraction of the area of TSSOP or VQFN translators, enabling dense sensor-cluster routing on 1.8V-to-3.3V boundaries. Typical links include sensor interrupt/enable lines, push-pull I2C-alternative buses, and chip-selects between a low-voltage application processor and 3.3V peripheral ICs. Because TXB outputs only consume power dynamically with signal activity, the translator adds negligible static load, supporting battery-life budgets. Layout teams must support DSBGA reflow and inspection, and should verify that sensor modules present push-pull outputs rather than open-drain with strong pull-ups, which would conflict with auto-direction sensing.
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Industrial Control and PLC I/O
Industrial logic commonly mixes 5V CMOS field-signal levels with 3.3V or lower-voltage controllers; the TXB0104YZTR safely bridges these domains with its 5.5V-tolerant B port and 1.2V-capable A port. The 100 Mbps rate covers fast enable, direction, and quadrature-encoder feedback lines, while -40C to +85C operation suits cabinet and floor-mounted equipment. The +/-15 kV IEC ESD rating provides extra margin near connectors and operator-accessible panels. For high-fanout backplane nets, designers should verify drive capability since TXB drivers are ~4 kOhm and intended for point-to-point links; heavier loads should use a stronger directional buffer instead. Two TXB0104 devices can translate two 4-bit clusters, or a TXB0108 covers an 8-bit bus.
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Consumer Display and Camera Modules
Camera and display modules frequently expose MIPI-adjacent control buses, I2C-adjacent push-pull control lines, and reset/interrupt GPIOs at 1.8V, while the host board's legacy control logic runs at 3.3V. The TXB0104YZTR translates four such signals in one micro-package placed directly at the flex-connector breakout, minimizing stub length and preserving signal integrity at rates up to 100 Mbps. Its automatic direction sensing suits shared control lines where direction changes mid-frame, and the ESD rating helps at board-edge interfaces. Engineers should route the translator within a few millimeters of the connector, use 0.1 uF decoupling on both VCCA and VCCB within 2 mm of the balls, and confirm module side outputs are push-pull rather than open-drain with sub-25 kOhm pull-ups.
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General-Purpose GPIO Voltage Bridging
For any board mixing logic families - a 1.2V FPGA bank talking to 3.3V sensors, or a 5V legacy device feeding a 1.8V MCU - the TXB0104YZTR offers a generic, firmware-free solution: no direction registers, no strobes, just power both rails and connect. The VCCA range down to 1.2V covers leading-edge FPGA and ASIC banks that many competing translators (typically 1.65V minimum) cannot reach, a decisive selection factor for low-voltage designs. Its TRUE output polarity and 13.7 ns delay are transparent to most GPIO timing. Keep the point-to-point discipline: one driver per side per net, loads under roughly 30 pF, and pull resistors above 25 kOhm, per TI's TXB0104 datasheet application guidance, to keep auto-direction sensing stable.
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추천 제품 요약
엔지니어링 참조 데이터: TXB0104YZTR — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | TXB0104PWRG4 | TXB0108YZPR2 |
|---|---|---|---|
| Package | 12-DSBGA (YZT) 1.9x1.4 mm | TSSOP-14 | 12-DSBGA (YZP), 8 channels |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments |
| Channels | 4 | 4 | 8 |
| Direction Control | Automatic | Automatic | Automatic |
| A Port Voltage Range | 1.2 V to 3.6 V | 1.2 V to 3.6 V | 1.2 V to 3.6 V |
| B Port Voltage Range | 1.65 V to 5.5 V | 1.65 V to 5.5 V | 1.65 V to 5.5 V |
| Max Data Rate | 100 Mbps | 100 Mbps | 100 Mbps |
| Drop-in Compatible | - | No (different package) | No (8-channel ballout) |
주요 차별점
- 1.2V minimum A-port support (vs TXB0104PWRG4)
- Auto direction sensing removes firmware burden (vs TXB0108YZPR2)
- +/-15 kV IEC ESD on I/O (vs TXB0104PWRG4)
설계 노트
The TXB0104 output stage uses approximately 4 kOhm mixed-charge-pump drivers optimized for point-to-point CMOS links. Keep per-net load capacitance low (about 30 pF or less) for clean 100 Mbps edges, avoid stubs, and never connect two TXB outputs back-to-back through a connector that can momentarily be driven from both sides - this is the classic TXB bus-contention failure mode described in TI's datasheet application section.
Do not use the TXB0104YZTR on open-drain buses such as I2C, or with external pull-up/pull-down resistors below about 25 kOhm: the auto-direction sensing interprets a low driven through a strong pull as the local side asserting, causing corruption or latch-like contention. For I2C use a dedicated open-drain translator instead. Also respect VCCA <= VCCB at power-up and use the OE pin to keep outputs tri-stated until both rails are stable.
For the 1.9 mm x 1.4 mm DSBGA-12 (0.5 mm pitch), use NSMD pads per TI datasheet land-pattern guidance, place 0.1 uF decoupling capacitors on VCCA and VCCB within 2 mm of the balls, and route VCCB-adjacent traces away from fast clock nets to avoid crosstalk into the auto-direction comparators. DSBGA requires reflow assembly with X-ray or optical inspection; hand rework is impractical, so panelize with spare sites.
Estimated: the TXB0104 consumes negligible static current with static I/O; its dominant consumption is dynamic, scaling with signal rate and load. At 100 MHz toggling into ~15 pF total per channel, dynamic charging is on the order of a few mA per device (P ~ C*V^2*f arithmetic). Budget supply rails accordingly but no heatsinking is ever required; ensure both rails respect VCCA <= VCCB to avoid internal path conduction during sequencing.
규정 준수 정보
RoHS compliance per TI product listing in verified web data. REACH, halogen-free, and conflict-minerals status not stated in provided data.
