UCD90320ZWST - 32-Rail PMBus Power Sequencer & System Manager | TI
부품 번호: UCD90320ZWST ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $16.76 | $16.76 |
| 10 | $15.78 | $157.80 |
| 100 | $14.2 | $1,420.00 |
| 500 | $12.65 | $6,325.00 |
| 1,000 | $11.4 | $11,400.00 |
UCD90320ZWST 개요
A power sequencer is a specialized supervisory IC that orchestrates the turn-on/turn-off order, timing, and fault response of multiple voltage rails. In the hierarchy of power-management ICs, sequencers sit above simple voltage supervisors (single-rail reset/watchdog) and below PMBus-configurable digital power controllers. They translate high-level system events into coordinated rail-by-rail actions using logic expressions, timers, and PMBus commands. The UCD90320 adds closed-loop monitoring, fault logging, and non-volatile configuration to that role.
Key features include flexible sequence-on and sequence-off dependencies based on delay time, Boolean logic, and GPIO triggers; full OV/UV/OC/UC/temperature/time-out/GPI-triggered fault detection; pin-selected rail states for up to 8 user-defined power states using 3 GPIs (supporting ACPI low-power modes); cascade-capable FAULT pin for synchronized fault responses across multiple devices; and on-chip non-volatile memory for configuration storage. The PMBus interface supports standard command set plus TI extensions for sequencing and fault response.
Architecturally, the UCD90320 combines a Cortex-M0-class configuration manager with a 24-channel sigma-delta ADC front end, a dedicated sequencing state machine, and an I2C/PMBus slave interface. The 0.8 mm-pitch BGA supports the high pin count required for 24 analog inputs, 84 GPIO, and PMBus/serial interface pins in a compact 12x12 mm outline.
Typical applications include FPGA/ASIC power-rail sequencing and supervision, ATCA/telecom board power management, server and storage-system boot sequencing, industrial multi-rail power distribution, and ACPI-compliant low-power state coordination. Use the UCD90320 Fusion Digital Power Designer GUI for offline configuration and the TI USB-to-GPIO adapter for in-system programming. When designing, always allocate sufficient bulk capacitance on monitored rails and verify ADC input dividers against the 6 V full-scale range.
드롭인 대체품: UCD90320ZWST — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
UCD90320ZWSR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
UCD90320ZWST
✅ 드롭인✓ 재고 있음
$11.4 / 개
데이터시트 보기 →UCD90320ZWST 사양
| 기능 | 32-rail PMBus power sequencer and system manager |
| Number of Monitored Voltage Rails | 24 (analog) + 8 (digital) |
| ADC Channels | 24 (AMONx) |
| GPIO Pins | 84 |
| Digital Monitor Pins (DMONx) | 8 |
| PMBus Interface | Yes (compliant to PMBus spec, with TI extensions) |
| Configuration Memory | Non-volatile on-chip |
| Fault Detection | OV, UV, OC, UC, temperature, time-out, GPI-triggered |
| Pin-Selected Power States | Up to 8 user-defined (via 3 GPIs) |
| Cascade Support | Yes (FAULT pin for synchronized fault response) |
| 패키지 | 169-ball NFBGA, 12 mm x 12 mm |
| Ball Pitch | 0.8 mm |
| 실장 유형 | Surface Mount (BGA) |
| RoHS 상태 | Compliant (per TI product page) |
UCD90320ZWST 169-ball nfbga, 12 mm x 12 mm 핀 구성 가이드
UCD90320ZWST(169-ball nfbga, 12 mm x 12 mm 패키지)의 핀 구성입니다. 핀 번호, 기능, 연결 다이어그램은 제조사 데이터시트에 정의되어 있습니다. 정확한 풋프린트와 솔더링 지침은 해당 문서를 참조하십시오.
다음에 대한 상세 핀아웃 데이터 없음: UCD90320ZWST.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
UCD90320ZWST 적합 용도: 6 애플리케이션s: FPGA/ASIC Multi-Rail Power Sequencing, Server and Storage System Boot Sequencing, Telecom and ATCA Board Power Management, Industrial Multi-Rail PLC and Motion Controllers, ACPI-Compliant Power-State Coordination, Test and Measurement Equipment.
FPGA/ASIC Multi-Rail Power Sequencing
The UCD90320ZWST sequences and supervises the 6 to 18 voltage rails typical of large FPGA or ASIC power trees. Its 24 analog AMONx ADC channels monitor each rail's voltage with per-rail OV/UV thresholds, and the dedicated FAULT pin coordinates synchronized shutdown across the regulator array. PMBus programmability lets the FPGA designer reconfigure sequencing and fault responses without hardware changes, accelerating bring-up.
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Server and Storage System Boot Sequencing
Servers require deterministic, ordered power-up of core, memory, I/O, and auxiliary rails. The UCD90320ZWST enforces up to 32 independent rails with delay-based, Boolean-logic, or GPI-triggered dependencies and stores the boot sequence in non-volatile memory for instant execution on power-up. The FAULT pin propagates system-wide fault responses across multiple cascaded UCD90320 devices, supporting ATCA-style card-management architectures.
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Telecom and ATCA Board Power Management
ATCA and AdvancedTCA shelves require hot-swap-friendly, intelligent power management. The UCD90320ZWST's PMBus interface provides the IPMC-compatible telemetry stream for board-management controllers, while its 24 analog monitors cover all payload voltages plus bias supplies. The 8 pin-selected power states implement ACPI S0-S5 transitions cleanly, satisfying telecom equipment power-state requirements.
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Industrial Multi-Rail PLC and Motion Controllers
Industrial PLCs combine isolated logic supplies, motor-driver rails, and analog I/O supplies that must come up in a precise order. The UCD90320ZWST supervises 24 analog rails and 8 digital rails, detecting under-voltage, over-current, and over-temperature faults within milliseconds. The non-volatile configuration enables factory-floor deployment without per-unit programming, while PMBus allows field diagnostics via the PLC's host CPU.
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ACPI-Compliant Power-State Coordination
The UCD90320ZWST implements up to 8 user-defined power states using 3 GPI inputs, mapping directly to ACPI S0 through S5 states. The device coordinates simultaneous rail ramp-down for sleep transitions and ordered wake-up on resume, all while maintaining fault supervision. This offloads power-state management from the host CPU, simplifying BIOS and OS-level power policy code.
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Test and Measurement Equipment
ATE and bench instruments often require 16 to 32 precision rails to power the DUT, signal-conditioning ASICs, ADCs, and DACs. The UCD90320ZWST sequences and monitors every rail with PMBus-readable telemetry, supporting automated production-test workflows. The 169-ball NFBGA package fits the compact, high-density PCBs typical of modern instruments, while on-chip non-volatile memory captures board-specific calibration constants.
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추천 제품 요약
엔지니어링 참조 데이터: UCD90320ZWST — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | UCD90320ZWSR |
|---|---|---|
| Package | 169-ball NFBGA 12x12 mm, 0.8 mm pitch | 169-ball NFBGA 12x12 mm - same |
| Brand | Texas Instruments | Texas Instruments |
| Number of Monitored Rails | 32 (24 analog + 8 digital) | 32 (24 analog + 8 digital) |
| GPIO Count | 84 | 84 |
| Pin-Selected Power States | 8 (via 3 GPIs) | 8 (via 3 GPIs) |
| Cascade FAULT Pin | Yes | Yes |
| PMBus Interface | Yes (with TI extensions) | Yes (with TI extensions) |
| Packaging Form | Tray (ZWS) | Tape and Reel (ZWSR) |
주요 차별점
- Highest rail count in TI UCD90xxx family (vs UCD90240)
- On-chip non-volatile configuration memory (vs Discrete supervisor + EEPROM designs)
- 8 pin-selected power states with ACPI support (vs GPIO-only sequencers)
설계 노트
The 169-ball NFBGA with 0.8 mm pitch requires laser-drilled or fine-pitch PCB fabrication. Use microvia-in-pad or stacked-microvia stackup with ENIG or immersion-silver finish. TI's UCD90320 datasheet (Rev. C) recommends a 4-layer or higher stackup with a continuous ground plane beneath the BGA to minimize thermal resistance and provide a low-impedance return path for the 24 ADC inputs.
Route AMONx (analog monitor) traces as differential pairs (positive and negative sense) directly from the monitored rail's output capacitors. Keep sense traces away from switching node edges (SW nodes of buck regulators) and use a ground guard trace or coplanar waveguide with ground pour. Per the UCD90320 datasheet (Rev. C), the ADC uses a 6 V full-scale range, so divider resistors must keep the worst-case monitored voltage below 6 V.
Do not hot-plug the UCD90320ZWST without sequencing its AVIN and DVIN rails - the device may latch up if the analog and digital supplies rise out of order. The UCD90320 datasheet (Rev. C) specifies the power-up sequencing: bring up AVIN first, then DVIN within 20 ms, or tie both rails together. Always verify the FAULT pin pull-up is present or the cascade logic may mis-trigger.
Place the 100 nF AVIN/DVIN decoupling capacitors within 2 mm of their respective BGA balls, and add a 10 uF bulk capacitor per supply rail. The PMBus SDA/SCL lines should be pulled up to the same 3.3 V rail that powers the device's DVIN domain, with a 10 kohm pull-up resistor. The UCD90320 datasheet (Rev. C) layout section shows the recommended thermal via array under the central balls to dissipate the ~0.5 W typical dissipation.
규정 준수 정보
RoHS compliance and lead-free status confirmed on the TI product page. REACH, halogen-free, and conflict-minerals declarations are not explicitly listed in the provided data and are marked 'unknown'.
