ADC/DAC
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LTC2344CUH-16 - Quad 16-Bit 400ksps/ch SoftSpan SAR ADC | Analog Devices
The Analog Devices LTC2344CUH-16 is a quad, 16-bit, 400 ksps per channel, simultaneous-sampling successive approximation register (SAR) analog-to-digital converter with differential, wide common-mode-range inputs, housed in a 32-pin QFN (5x5) package. Each channel features a flexible SoftSpan input range from ±10.24V down to 0V to 5.12V set on a per-conversion basis, ±1.25 LSB INL, 93.4 dB SNR, 102 dB CMRR, and guaranteed no-missing-codes at 16-bit resolution. The device operates from a single 5V analog supply and a 1.8V to 5V digital supply, supporting both SPI CMOS and LVDS serial interfaces selectable per lane. What is a SAR ADC? A successive-approximation-register analog-to-digital converter is a precision data converter that performs a binary search through an internal capacitive network, comparing the sampled input against an internal DAC one bit per clock cycle to converge on the digital output. SAR ADCs sit in the broader ADC family alongside delta-sigma, pipeline, and flash converters; they offer an excellent balance of resolution (16-20 bits), sampling rate (100 ksps to multi-MB ms), latency (single-cycle, deterministic), and power consumption, which is why they dominate multiplexed data-acquisition, industrial instrumentation, and high-speed control-loop applications. Key features include per-channel independent input ranges, true simultaneous sampling across all four ADCs, an integrated precision reference and reference buffer, pin-selectable SPI/LVDS interface, and configurable one-to-four-lane CMOS output for bus-width optimization. The combination of 93.4 dB SNR and 102 dB CMRR allows the part to directly digitize wide common-mode signals in noisy industrial environments without front-end signal conditioning. Typical applications include industrial process control and multichannel data acquisition systems, medical instrumentation such as patient monitoring and ECG/EMG front ends, optical networking, and multi-axis motor control. The simultaneous-sampling architecture is particularly valuable in three-phase power monitoring and vibration analysis where channel-to-channel phase relationships must be preserved. When designing with this device, place the internal reference bypass capacitor and decoupling capacitors close to the pins and follow the Analog Devices reference layout for the exposed pad. The SoftSpan per-channel range control requires writing the range register between conversions, which must be accounted for in software timing. Pricing and availability data are quoted as of 2026-10-13. This page synthesizes distributor stock, drop-in same-package alternatives, and design considerations not collected in the manufacturer datasheet alone.
LTC2344CUH-18 - 18-Bit 400kSPS Quad SAR ADC | Analog Devices
The Analog Devices LTC2344CUH-18 is an 18-bit, 400 kSPS per channel, simultaneous-sampling 4-channel SAR analog-to-digital converter with differential, wide common-mode-range SoftSpan front ends, packaged in a 32-pin QFN (5x5 mm) with exposed pad. Operating from a single 5 V supply, the device integrates a precision internal reference and buffer, plus a per-channel sample-and-hold, enabling true simultaneous acquisition across four channels without inter-channel latency. A successive approximation register (SAR) ADC is a precision data converter architecture that resolves one bit per clock cycle using a binary-weighted capacitor DAC and a comparator, then digitizes the input through a successive approximation search. SAR ADCs are valued for low latency, deterministic behavior, no pipeline latency, and excellent DC accuracy. Within the converter family hierarchy, SAR ADCs sit below pipelined ADCs (higher speed, higher channel count) and delta-sigma ADCs (highest resolution, lowest bandwidth); the LTC2344 family targets the mid-bandwidth, multi-channel, high-precision industrial segment. Key specifications include 18-bit resolution with no missing codes, 400 kSPS per channel simultaneous sampling rate, four differential SoftSpan inputs accepting true bipolar ±10.24 V or 0-5 V ranges, 100 dB SNR typical, and ±2 LSB INL maximum. The serial interface supports pin-selectable SPI CMOS (1.8 V to 5 V) or LVDS output, with one to four lanes selectable in CMOS mode to optimize bus width and throughput. The internal 2.048 V reference and buffer reduce external component count. Typical applications include industrial process control and automation, multi-channel data acquisition systems, medical imaging front ends, instrumentation and test equipment, and high-speed multichannel precision monitoring. The 32-QFN package with exposed pad provides low thermal resistance suitable for continuous high-throughput conversion. When designing, decouple AVDD/DVDD/OVDD with 1 µF and 0.1 µF ceramic capacitors placed as close to the pins as possible. Drive the CNV rising edge to start conversion; route the LVDS or CMOS data lines with controlled impedance and length-matching. The exposed pad must be soldered to a continuous ground plane for thermal dissipation and low-impedance return paths. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone manufacturer datasheet.
LTC2344HUH-16 - 16-Bit 4-Ch 400ksps SoftSpan SAR ADC | ADI
The Analog Devices LTC2344HUH-16 is a 16-bit, low-noise, 4-channel simultaneous-sampling successive-approximation-register (SAR) analog-to-digital converter with differential, wide common-mode-range inputs, delivered in a 32-pin QFN (5x5 mm) package. Each of the four channels samples at up to 400 ksps, and the part operates from a single 5 V analog supply with an internal reference and internal reference buffer, eliminating the need for external precision reference components. A SAR ADC (Successive Approximation Register analog-to-digital converter) is a type of precision data converter that performs one binary bit decision per clock cycle using an internal capacitive DAC, a comparator, and a successive-approximation register. Within the broader signal-chain hierarchy, the LTC2344-16 belongs to the precision SAR ADC family, which sits between high-speed pipeline ADCs and lower-power delta-sigma ADCs, offering a balance of latency, channel count, and DC accuracy. ADI's SoftSpan™ technology allows per-conversion, per-channel selection of the analog input range, optimizing dynamic range across all four channels. Key features of the LTC2344HUH-16 include pin-selectable SPI CMOS (1.8 V to 5 V) or LVDS serial interfaces, 1 to 4 lanes of CMOS data output, 102 dB CMRR, ±1.25 LSB INL, no missing codes at 16 bits, 93.4 dB SNR, and an operating temperature range of -40 °C to +125 °C. The wide common-mode input range and high CMRR allow the analog inputs to directly digitize a variety of signals - including those riding on top of large DC bias or AC common-mode voltages - simplifying the front-end signal chain by removing driver amplifiers and level-shifters in many applications. Architecturally, each channel uses a precision charge-redistribution capacitive DAC combined with an internal low-drift reference and a high-CMRR input front end, enabling simultaneous sampling of all four channels with matched aperture delay. Throughput and bus width are software-configurable: in CMOS mode the user may select 1, 2, or 4 LVDS lanes, while in LVDS mode the converter delivers full 400 ksps/channel throughput to modern FPGAs. The integrated reference buffer preserves low noise and high PSRR even when multiple channels are sampling simultaneously, making the LTC2344HUH-16 well suited for multi-axis data-acquisition systems. Typical applications include multi-axis motor and motion control, industrial process control, test and measurement instrumentation, seismic and energy-exploration data acquisition, and high-speed medical imaging front ends. The combination of true simultaneous sampling, wide common-mode range, and per-channel span switching makes it especially attractive for multi-phase power-conversion feedback, vibration analysis, and phased-array sensor systems. When designing with the LTC2344HUH-16, ensure that the analog inputs remain within the datasheet common-mode and differential range for the selected SoftSpan range, and follow ADI's recommended layout for the exposed pad (EP) to maintain thermal performance and low digital crosstalk. Decouple the 5 V AVDD and the digital DVDD rails with low-ESR ceramic capacitors placed as close to the IC as possible. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, with data verified as of 2026-10-13.
LTC2344HUH-18 - 18-Bit Quad SAR ADC, 400ksps/ch | Analog Devices
The Analog Devices LTC2344HUH-18 is a quad, 18-bit, 400 ksps per channel differential SoftSpan successive approximation register (SAR) analog-to-digital converter (ADC) housed in a 32-pin QFN (5x5 mm) exposed-pad package. Each of the four simultaneous-sampling channels integrates a precision SAR core, an internal 2.048V reference, and a wide common-mode input stage that accepts differential inputs spanning rail-to-rail (0V to VREF or 0V to 2*VREF), making the part suitable for high-density data acquisition boards where PCB real estate is at a premium. A SAR ADC is a successive-approximation analog-to-digital converter: it performs one bit-trial per clock cycle against an internal capacitive DAC, converting analog input to digital code in N cycles for N bits of resolution. SAR ADCs combine low latency, deterministic behavior, and excellent DC accuracy, which is why they dominate multi-channel precision instrumentation, oscilloscope digitizers, and industrial process-control front ends. The LTC2344-18 sits in the hierarchy: SAR ADC -> ADC -> data converter -> signal chain IC -> semiconductor. Key features include 4 differential simultaneous-sampling inputs, software-configurable per-channel input range (SoftSpan from ±10.24V to 0V–5V using internal reference scaling), pin-selectable SPI CMOS (1.8V to 5V) or LVDS serial interfaces, and 1 to 4 CMOS output lanes for bus-width optimization. Typical SNR of 95 dBFS and INL of ±2.5 LSB (max) support demanding measurement-grade applications. The architecture pairs an analog 5V supply (AVDD) with a separate digital 1.8V to 5V supply (OVDD), allowing the ADC to digitize ±10V signals while directly interfacing to low-voltage FPGAs or microcontrollers. The internal reference and reference buffer reduce BOM count by eliminating external REF02-class components. Typical applications include multi-axis motor control feedback, programmable logic controller (PLC) analog input modules, data acquisition systems (DAQ), instrumentation and test equipment, and high-precision multi-channel sensor signal conditioning. The wide common-mode range simplifies level shifting when digitizing bridge sensors, thermocouples, or current-sense amplifiers referenced to a mid-supply. When designing with this part, place the analog and digital decoupling capacitors as close as possible to AVDD and OVDD pins, and provide a solid ground plane beneath the exposed pad to keep the thermal resistance (around 40 C/W) within bounds. The SoftSpan input range should be configured per channel after the conversion starts; the LVDS interface option requires a 100 ohm termination at the receiver. This page synthesizes distributor pricing, drop-in same-package alternatives drawn from the Analog Devices LTC23xx family, and practical design notes that complement the manufacturer's datasheet.
LTC2345CUK-18 - Octal 18-bit 200kSps Diff SoftSpan ADC | ADI
The Analog Devices LTC2345CUK-18 is an octal, 18-bit, 200 kSps differential SoftSpan successive approximation register (SAR) analog-to-digital converter housed in a 48-lead QFN (7x7) package. It delivers ±5 LSB INL, no missing codes at 18-bit resolution, and 91.8 dB SNR across eight differential input channels with wide input common-mode range. The device supports pin-selectable SPI CMOS (1.8 V to 5 V) and LVDS serial interfaces for flexible digital connectivity. Operating from a single 5 V low-voltage supply with integrated reference and buffer, the part is tailored to wide-input-range multi-channel data acquisition. A SoftSpan ADC is a successive approximation converter whose input voltage range can be reconfigured on a per-conversion, per-channel basis via internal programmable gain stages. Within the data-converter hierarchy, SAR ADCs sit between flash converters (fastest, lowest resolution) and sigma-delta ADCs (highest resolution, lower bandwidth). The LTC2345CUK-18 occupies the multi-channel, medium-resolution, low-latency niche where simultaneous acquisition of several signals is required without the latency penalty of sigma-delta. Key differentiating features include eight truly differential input channels sampled through an 8-channel simultaneous-sampling front end, per-conversion SoftSpan range selection across multiple bipolar and unipolar spans, and an integrated 2.048 V reference with buffer that eliminates external reference components. The QFN-48 (UK suffix) 7x7 mm package with exposed pad provides a low thermal resistance path and compact PCB footprint. Typical applications include multi-axis industrial process control, multi-channel instrumentation, optical networking power monitoring, and programmable logic controller (PLC) analog front ends. The simultaneous-sampling capability is decisive in phased-array and vibration analysis where channel-to-channel skew would corrupt the measurement. As of 2026-10-13 pricing is held in distributor stock at DigiKey, Mouser, and authorized partners. When designing with the LTC2345CUK-18, ensure the exposed pad is soldered to a continuous ground plane for thermal dissipation and reference decoupling. Reject NMC pins by tying them to known logic levels per the datasheet, and route the LVDS or SPI traces as 50 ohm controlled-impedance differential lines if LVDS mode is selected. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the standalone manufacturer datasheet.
LTC2348CLX-16 - Octal 16-Bit 200ksps SAR ADC | Analog Devices
The Analog Devices LTC2348CLX-16 is an octal, 16-bit, 200ksps per-channel simultaneous-sampling successive approximation register (SAR) ADC with differential inputs and a wide input common-mode range, packaged in a 48-pin LQFP (7x7). It features eight independent SoftSpan inputs that can each be reconfigured on a per-conversion basis, integrated precision buffers, an internal reference, and a 5V low-voltage analog supply with flexible high-voltage supplies for the input front-end. The wide common-mode range and 118dB CMRR allow the analog inputs to directly digitize a variety of industrial signal levels without external level translation. A successive approximation register ADC is a precision data converter architecture that performs a binary search on the input voltage using a high-precision DAC and comparator to produce a digital code in N conversion cycles for N bits of resolution. SAR ADCs are valued for low latency, no pipeline delay, excellent DC accuracy, and inherent per-sample determinism, which makes the LTC2348 family particularly well suited to multi-channel data-acquisition systems where eight channels must be sampled synchronously to preserve phase and amplitude relationships. SoftSpan further extends the architecture by allowing each channel's input range to be reconfigured cycle-by-cycle to one of several software-selectable spans. Key specifications include 16-bit resolution with no missing codes, +/-1LSB INL (max), 94.4dB SNR, and 200ksps throughput per channel on all eight channels simultaneously. The differential wide-common-mode input structure supports +/-10.24V true bipolar signals when paired with the appropriate high-voltage supply, and the device provides per-channel input span reconfiguration for mixed-range acquisition. Integrated reference and buffer simplify the analog supply tree and reduce external BOM. In multi-channel industrial applications, the simultaneous-sampling SAR topology captures all eight channels in lock-step with sub-microsecond aperture timing, eliminating inter-channel skew that would otherwise corrupt phase-sensitive measurements. Designers can pair the converter with an FPGA or DSP for digital signal processing, and leverage the SoftSpan range reconfiguration to mix high-level and low-level sensors on a single ADC chip. When laying out the PCB, keep analog input traces short and symmetric, place the internal reference decoupling capacitor close to the REF pin, and provide a solid ground plane under the LQFP body. Use a dedicated low-noise LDO for the 5V analog rail and isolate it from digital switching supplies to preserve the 94.4dB SNR. This page synthesizes distributor pricing, drop-in alternative MPNs, and practical design notes not found in the manufacturer datasheet, giving engineers a single source for both selection and design-in guidance.
LTC2348HLX-16 - Octal 16-Bit 200ksps SAR ADC | Analog Devices
The Analog Devices LTC2348HLX-16 is a 16-bit, low-noise, 8-channel simultaneous sampling successive approximation register (SAR) analog-to-digital converter (ADC) with differential, wide common-mode range inputs, housed in a 48-pin LQFP (7x7) package. It supports ±10.24 V true bipolar SoftSpan inputs, 200 ksps per channel throughput, and 94.4 dB SNR with 118 dB CMRR per the manufacturer datasheet. A successive approximation register (SAR) ADC is a type of data converter that performs a binary search to digitize an analog input one bit at a time using an internal capacitive DAC and a comparator. SAR ADCs are prized for low latency, deterministic latency, and excellent DC accuracy, occupying a middle position in the converter hierarchy: SAR ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor. The LTC2348 family is positioned for high-precision multi-channel applications where simultaneous sampling across channels is required, such as in polyphase power metering and multi-axis industrial control. Key features include independent per-channel SoftSpan input ranges (±10.24 V, 0 V to 10.24 V, ±5.12 V, 0 V to 5.12 V, and additional ranges), a wide input common-mode range that allows direct digitization of many signals without front-end signal conditioning, ±1 LSB INL with no missing codes at 16 bits, and an internal 2.048 V reference with buffer. The 48-pin LQFP-48 (7x7) package exposes separate analog and digital supply pins (4.75 V to 5.25 V), an SPI-compatible serial interface, and an extended automotive temperature grade of -40 °C to +125 °C per the H-grade designation. The architecture uses eight simultaneous-sample-and-hold front ends that capture all channels on the same CONVST rising edge, eliminating inter-channel skew. A flexible external or internal reference and a per-channel sequencer allow each of the eight conversions to be configured independently, simplifying systems where channel ranges differ across a single scan. Typical applications include polyphase energy and power metering, multi-axis motor control and industrial PLC analog front ends, data acquisition systems with high common-mode voltages, and medical instrumentation requiring simultaneous sampling. Because each channel can be independently ranged, a single LTC2348-16 can replace multiple ADCs in mixed-voltage systems. When designing with this part, place the analog and digital decoupling capacitors as close as possible to their respective supply pins and route the analog and digital grounds back to a single point to preserve the 94.4 dB SNR. The internal reference and buffer simplify BOM cost, but designers who need lower drift across temperature can disable the buffer and drive REFIN with an external low-noise reference. This page synthesizes verified distributor pricing, drop-in pin-compatible alternatives drawn from the same LQFP-48 family, and practical PCB/grounding design notes that go beyond the manufacturer datasheet block diagram.
LTC2348HLX-18 - 18-Bit Octal SAR ADC, 200ksps, 48-LQFP | ADI
The Analog Devices LTC2348HLX-18 is an 18-bit, low-noise, 8-channel simultaneous-sampling successive approximation register (SAR) ADC with differential, wide common-mode-range inputs, offered in a 48-lead LQFP (7x7 mm) package. Each of the eight channels samples at up to 200 ksps and delivers 96.7 dB SNR with ±3 LSB INL and no missing codes at 18 bits. What is a SAR ADC? A successive-approximation-register analog-to-digital converter is a precision data-conversion architecture that uses a binary-search algorithm against an internal DAC to resolve an analog input one bit at a time. SAR ADCs sit in the signal-chain hierarchy between flash converters (fastest, lowest resolution) and sigma-delta converters (highest resolution, lower speed), and are prized for their deterministic latency, excellent DC accuracy, and low power per conversion. The octal simultaneous-sampling topology extends this precision to multi-axis or multi-phase systems by guaranteeing that all eight channels capture the same instant in time. Key features include pin-selectable SoftSpan input ranges on a per-channel, per-conversion basis, ±10.24 V true-bipolar differential inputs with 118 dB CMRR, an internal 2.048 V reference with 2X buffer (external reference supported), and a serial interface selectable between 1.8 V to 5 V CMOS SPI and LVDS with one to eight output lanes. The wide common-mode input range allows the ADC to directly digitize signals riding on high voltages, eliminating external level-shift circuitry in many applications. The architecture combines eight simultaneously-sampling track-and-hold front-ends with a shared SAR core, internal reference/buffer, and configurable logic. SoftSpan allows the user to switch input ranges per conversion, optimizing dynamic range channel-by-channel, while the wide common-mode range and 118 dB CMRR simplify the analog front-end for industrial signal chains. Typical applications include multi-axis motor control and servo drives, three-phase power-quality monitoring, simultaneous-sampled data acquisition (DAQ) modules, medical multi-channel instrumentation, and ATE pin electronics. The wide input common mode and bipolar ranges make it well-suited to industrial 24 V / ±15 V signal environments. A primary design consideration is power-supply sequencing: the LTC2348HLX-18 requires a 5 V low-voltage supply and flexible high-voltage supplies. Decoupling must be placed close to each supply pin, and reference bypass capacitors must follow the datasheet's recommended network to achieve the rated 96.7 dB SNR. This page synthesizes distributor pricing, drop-in same-package alternatives from the LTC2348 family, and practical design notes not aggregated in a single location on the manufacturer's datasheet.
LTC2351CUH-14 - 14-Bit 1.5Msps 6-Ch Simultaneous-Sampling ADC | ADI
The Analog Devices LTC2351CUH-14 is a 14-bit, 1.5Msps analog-to-digital converter (ADC) with six simultaneously sampled differential inputs, housed in a 32-pin QFN (5mm x 5mm) package. It draws only 5.5mA from a single 3V supply, and a sleep shutdown mode further reduces power consumption to 12uW, making it ideal for portable and multi-channel data-acquisition systems. An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete digital codes for processing by microcontrollers, DSPs, or FPGAs. Multi-channel simultaneous-sampling ADCs such as the LTC2351CUH-14 are a specialized subclass of successive-approximation-register (SAR) ADCs designed for applications where the relative phase between channels must be preserved — for example, three-phase power monitoring, multi-axis vibration analysis, and phased-array beamforming. The LTC2351CUH-14 belongs to the power management and signal-chain IC hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. Key features of the LTC2351CUH-14 include six differential input channels sampled simultaneously at up to 1.5Msps per channel, a single 3V analog supply operation, 12uW sleep-mode power, and an integrated track-and-hold per channel. The device accepts differential inputs well suited to bridge sensors, current shunts, and direct connection to operational amplifiers. Its 32-lead 5x5mm QFN package provides a compact footprint suitable for portable instrumentation and high-density PCB layouts. The LTC2351CUH-14 is built on a low-power CMOS SAR architecture with internal reference and six dedicated sample-and-hold amplifiers that capture all channel voltages on the same clock edge, eliminating inter-channel skew. A standard SPI/serial interface streams conversion results to the host controller, and a dedicated CONVST pin initiates conversion across all six channels synchronously. Typical applications include three-phase power-quality monitoring, multi-axis industrial vibration analysis, portable medical instrumentation, simultaneous multi-sensor data acquisition, phased-array ultrasound receivers, and multi-channel sonar / radar front-ends. The wide dynamic range and low power make the part suitable for both battery-powered and line-powered instruments. When designing with the LTC2351CUH-14, ensure the analog input common-mode voltage lies within the input range of the SAR core, and add anti-alias filtering on each differential pair. Decouple the 3V analog supply with a 10uF ceramic + 0.1uF X7R combination placed within 5mm of the supply pin to minimize ADC reference noise and improve spurious performance. This page synthesizes verified distributor pricing, drop-in alternative MPNs, and practical design notes drawn from the manufacturer datasheet and reference designs - content not consolidated on distributor product pages.
LTC2351CUH-14#PBF - 14-Bit 1.5Msps 6-Ch Simultaneous-Sampling ADC | ADI
The Analog Devices LTC2351CUH-14#PBF is a 14-bit, 1.5 Msps analog-to-digital converter with six simultaneously sampled differential inputs, housed in a 32-pin (5 mm x 5 mm) QFN package. It draws only 5.5 mA from a single 3 V supply and features a sleep shutdown mode that reduces power consumption to 12 uW, making it well suited for portable and multi-channel data-acquisition applications. Per the manufacturer datasheet, the device integrates six independent sample-and-hold amplifiers followed by a single shared 14-bit successive-approximation ADC core that sequentially converts each held channel at the full 1.5 Msps conversion rate. A SAR (Successive Approximation Register) ADC is a type of data converter that converts an analog input into a digital code by iteratively comparing the input against a precision DAC and a reference voltage. In system hierarchy, the LTC2351-14 belongs to: SAR ADC -> ADC -> data converter -> signal chain IC -> analog/mixed-signal semiconductor. SAR ADCs are valued for their deterministic latency, lack of pipeline delay, and excellent DC accuracy, which makes the simultaneous-sampling variant especially useful when the relative phase between channels must be preserved (such as in three-phase power metering or vibration analysis). Key features include six differential inputs sampled on the same clock edge (preserving inter-channel phase), a serial LVCMOS-compatible interface, an internal 2.5 V reference (with provision for an external reference), and an input common-mode range that accommodates both unipolar and bipolar signals when paired with appropriate driver circuits. The 32-lead QFN package provides a low thermal-resistance path and a compact 5 mm x 5 mm footprint suitable for space-constrained PCB designs. Typical applications include multiphase power monitoring, industrial process control and instrumentation, portable and handheld test gear, simultaneous data acquisition systems, vibration and modal analysis, and motor control feedback. The wide input common-mode range and differential architecture also simplify connection to bridge sensors and current-shunt monitors. A practical design tip is to place 0.1 uF ceramic bypass capacitors close to each supply pin and to keep the analog input traces short and symmetric, because aperture-time mismatch between channels at 1.5 Msps can otherwise manifest as inter-channel skew that degrades phase-sensitive measurements. This page synthesizes distributor pricing, drop-in alternatives, and design notes not found in the manufacturer datasheet, giving engineers a single source for evaluating, sourcing, and laying out the LTC2351CUH-14#PBF.
LTC2351CUH-14#TRPBF - 14-Bit 1.5Msps 6-Ch SAR ADC | Analog Devices
The Analog Devices LTC2351CUH-14#TRPBF is a 14-bit, 1.5 Msps successive-approximation analog-to-digital converter with six simultaneously-sampled differential input channels, housed in a 32-pin QFN (5 mm x 5 mm) package. The device operates from a single 3 V supply, drawing only 5.5 mA, and integrates a per-channel sample-and-hold amplifier so all six channels are sampled on a single CONV rising edge. A successive-approximation register (SAR) ADC is a precision data converter that performs a binary search against an internal DAC on each conversion cycle. Unlike pipeline or delta-sigma ADCs, SAR converters deliver a single-cycle latency with no digital filtering delay, making them well suited to multiplexed data acquisition, motor control loops, and multi-phase power monitoring where the relative timing between channels must be preserved. The LTC2351-14 family is positioned within Analog Devices' precision SAR product line for low-power, multi-channel, simultaneous-sampling applications. Key specifications include 14-bit resolution, 1.5 Msps per-channel throughput, six differential inputs sampled simultaneously, 5.5 mA typical supply current at 3 V, and an integrated shutdown mode that drops quiescent power to 12 uW. The 32-pin QFN (5x5) package provides a compact footprint and low thermal resistance for portable and densely-populated PCBs. Each channel features its own dedicated S/H amplifier, eliminating the skew between channels that would otherwise occur with a multiplexer-front-end architecture. Architecturally, the LTC2351-14 uses a capacitive charge-redistribution DAC core with an inherent sample-and-hold on every channel. The device accepts bipolar differential inputs of up to +/-2.048 V when using the on-chip reference and 3 V supply, or larger true bipolar ranges with an external reference. The serial LVTTL interface outputs the conversion result and per-channel data framing, simplifying connections to FPGAs, DSPs, and microcontrollers. Typical applications include industrial multi-phase power metering, three-phase motor control, simultaneous vibration and acoustic monitoring, multi-axis instrumentation, portable medical data acquisition, and any system that requires synchronized sampling across multiple analog inputs. The low 5.5 mA supply current also enables battery-powered multi-channel data loggers. When designing with this part, bypass the VDD pins with 10 uF and 0.1 uF ceramic capacitors placed as close to the package as possible, keep analog and digital grounds separated back at a single star point under the exposed pad, and tie the exposed paddle to analog ground for lowest noise. Driving the CONV input with a clean, low-jitter edge is essential to preserving simultaneous-sampling accuracy across channels. This page consolidates distributor stock and price data, drop-in same-package alternatives, and practical design notes drawn from the manufacturer datasheet and reference designs - information gain not bundled on the OEM datasheet alone.
LTC2351HUH-14#TRPBF - 14-Bit, 1.5Msps, 6-Ch Simultaneous-Sampling ADC | Analog Devices
The Analog Devices (formerly Linear Technology) LTC2351HUH-14#TRPBF is a 14-bit, 1.5 Msps analog-to-digital converter (ADC) with six simultaneously sampled differential inputs, housed in a 32-pin QFN (5 mm x 5 mm) package. Operating from a single 3 V supply, the device draws only 5.5 mA and integrates six track-and-hold amplifiers plus a 14-bit successive-approximation register (SAR) ADC core to preserve phase information across all six channels. A simultaneous-sampling SAR ADC is a converter that captures multiple analog channels on a common sampling edge, eliminating the inter-channel time skew inherent to multiplexed ADCs. Within the power-management IC family, the LTC2351 belongs to the data-converter hierarchy: ADC -> successive-approximation ADC -> simultaneous-sampling SAR ADC -> integrated multi-channel data acquisition IC. This category is foundational for any application that requires precise temporal correlation between multiple analog signals. Key specifications include a 1.5 Msps aggregate throughput, 5.5 mA typical supply current, 12 uW sleep-mode shutdown current, and six true-differential input channels. The device supports a single 3 V analog supply and includes an internal 2.5 V reference (with optional external reference drive), along with a serial LVCMOS-compatible interface that simplifies the digital connection to FPGAs, DSPs, or microcontrollers. Architecturally, each of the six input channels has its own dedicated track-and-hold amplifier that samples on the same CONVST edge, then sequentially converts through the shared 14-bit SAR core. This topology preserves full-scale input range while keeping the die small and power consumption low compared with six discrete ADCs. The integrated 2.5 V reference can be overdriven with an external reference for applications requiring tighter absolute accuracy or higher stability. Typical applications include three-phase power metering and motor-control feedback, multi-axis industrial motion control, portable and battery-powered instrumentation, and simultaneous multi-channel data acquisition boards. The combination of low 5.5 mA supply current and 12 uW sleep mode makes the LTC2351 especially attractive for handheld, energy-conscious designs. When designing with this ADC, place the AVCC decoupling capacitors within a few millimeters of the supply pins and keep the analog input traces short and symmetric to preserve common-mode rejection. Use the sleep (SHDN) pin aggressively between conversion bursts in low-duty-cycle applications to drop system consumption to the 12 uW range, which is roughly 460x lower than the active 5.5 mA. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical PCB-layout design notes not collected in the manufacturer datasheet, giving engineers a single reference for evaluation and sourcing.
LTC2355IMSE-12 - 12-Bit 3.5Msps Serial ADC | Analog Devices
The Analog Devices LTC2355IMSE-12 is a 12-bit, 3.5Msps successive approximation register (SAR) analog-to-digital converter with a single differential input channel, housed in a 10-pin MSOP-EP (exposed pad) package. It operates from a single 3.3V supply, drawing only 5.5mA, and features an integrated 2.5V internal bandgap reference for ratiometric or absolute measurements. An ADC (Analog-to-Digital Converter) is a data converter that samples continuous analog signals and quantizes them into discrete digital codes. SAR ADCs use a successive-approximation algorithm with an internal DAC and comparator, delivering deterministic latency, low power, and excellent DC accuracy - making them the dominant architecture for industrial, instrumentation, and precision sensor applications that require kilo-sample to mega-sample rates without the complexity of pipeline or sigma-delta converters. Key features include 3.5Msps conversion rate, 71.1dB SINAD at 12 bits, 18mW power dissipation, and a Sleep shutdown mode that reduces consumption to 13uW between conversions. The serial interface simplifies PCB routing and minimizes digital switching noise coupling back into the analog front end. The 10-pin MSOP-EP footprint with an exposed thermal pad provides low thermal resistance and a compact 3mm x 3mm board area. Typical applications include industrial process control, multi-channel data acquisition front ends, portable or battery-powered instrumentation, motor control feedback loops, and optical sensor monitoring. The differential input rejects common-mode noise in long cable runs or noisy industrial environments. When designing with this ADC, provide a low-impedance input driver (typically an op-amp buffer) and bypass the supply with 0.1uF and 10uF ceramic capacitors placed close to the AVdd pin. The exposed pad must be soldered to a sufficient copper pour for thermal dissipation and low-impedance ground return.
LTC2355IMSE-14 - 14-bit 3.5Msps SAR ADC | Analog Devices
The Analog Devices LTC2355IMSE-14 is a 14-bit, 3.5Msps serial successive-approximation-register (SAR) analog-to-digital converter (ADC) with differential inputs, housed in a 10-lead MSOP package with an exposed pad. It draws only 5.5mA from a single 3.3V supply and supports a 0V to 2.5V unipolar differential input range with 80dB common-mode rejection. A SAR ADC is a type of analog-to-digital converter that uses an iterative binary-search algorithm against a precision DAC to digitize an analog signal in a single conversion cycle, requiring no pipeline latency. SAR ADCs sit within the broader category of data converters, between sigma-delta ADCs (highest resolution, lowest speed) and flash ADCs (lowest resolution, highest speed). This places SAR converters in the middle of the trade-off space, offering high accuracy at moderate speeds with deterministic latency, which is critical for multiplexed data acquisition, motor control feedback, and instrumentation loops. The LTC2355-14 delivers 71.1dB SINAD at 14-bit resolution and 74.2dB SINAD at 12-bit resolution, giving designers flexibility to trade resolution for dynamic range. A Sleep shutdown mode reduces quiescent current to just 13uW, and the on-chip 2.5V internal bandgap reference can be overdriven by an external reference when higher accuracy or temperature stability is required. Power dissipation is only 18mW at full speed, which is exceptionally low for the sample-rate class. Typical applications include portable high-speed data acquisition, multiplexed sensor front-ends, industrial process control, and battery-powered instrumentation. The combination of small footprint, low power, and differential input architecture suits space-constrained designs where ground-loop immunity is required, such as isolated sensor digitizers and handheld test equipment. When designing with this part, place the 10uF bypass capacitor and 0.1uF decoupling capacitor as close as possible to the supply pins and bond the exposed pad (Pin 11) to a continuous ground plane to achieve the rated thermal and AC performance. Avoid driving the analog inputs above the supply rail to prevent input-protection conduction. This page synthesizes distributor pricing, cross-brand drop-in alternatives, and practical PCB layout guidance not consolidated on the manufacturer datasheet, giving a one-stop reference for engineers selecting the LTC2355IMSE-14.
LTC2358HLX-18#PBF - 18-Bit 200ksps/Ch Octal SAR ADC | Analog Devices
The Analog Devices LTC2358HLX-18#PBF is a buffered, 8-channel simultaneous-sampling, 18-bit successive approximation register (SAR) analog-to-digital converter rated at 200 ksps per channel, housed in a 48-pin LQFP (7x7 mm) package with exposed pad. Each channel integrates a picoamp-input analog buffer, a wide common-mode range front end, and 128 dB CMRR, enabling direct digitization of ±10.24 V true bipolar and 30 V_P-P common-mode signals without external signal conditioning. A SAR ADC is a successive-approximation-register converter that resolves one bit per clock cycle using a binary-search algorithm against a precision DAC. SAR ADCs occupy the middle ground between delta-sigma (high resolution, low speed) and flash (very fast, low resolution) converters, and are preferred for multi-channel data acquisition where deterministic per-channel latency and low latency-to-sample ratios matter. The LTC2358 family sits in the multi-channel simultaneous-sampling SAR segment alongside the Linear Technology legacy octal ADCs, offering per-channel independent SoftSpan range control. Headline specifications include 96.4 dB SNR, ±3.5 LSB INL (max), no missing codes at 18 bits, 128 dB CMRR, and pin-selectable SPI CMOS (1.8 V to 5 V) or LVDS serial interfaces with one to eight output lanes in CMOS mode. The internal reference and buffer remove the need for an external reference IC, while flexible high-voltage analog supplies accept rails from 5 V up to ±18 V or 0 V to 38 V. The architecture combines a switched-capacitor charge-redistribution DAC core with per-channel input buffers that present a very high impedance to the signal source, eliminating the loading effects and kickback currents typical of unbuffered SAR inputs. The SoftSpan interface allows each channel's input range to be reconfigured on a per-conversion basis between soft-span ranges from ±10.24 V down to 0 V to 5 V, trading full-scale range for noise density. Typical applications include multi-axis industrial position and pressure data acquisition, multi-phase power and energy metering, optical and analytical instrumentation, and any high-channel-count simultaneous-sampling test system requiring 18-bit resolution. The wide common-mode range makes it suitable for direct connection to bridges, RTDs, thermocouples, and current-shunt monitoring networks. When designing with this device, allocate the exposed pad to a continuous ground copper pour to maintain junction temperature within the -40 °C to +125 °C operating range, and follow Analog Devices' recommended layout for the analog and digital supply decoupling networks. The LVDS interface requires 100 Ω termination at the receiver end; CMOS mode requires level shifters if interfacing to a 1.8 V host. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that are not available in the manufacturer datasheet alone.
LTC2360CTS8 - 12-Bit 100ksps SAR ADC, TSOT-23-8 | Analog Devices
The Analog Devices LTC2360CTS8 is a 12-bit, 100 ksps successive-approximation-register (SAR) analog-to-digital converter (ADC) housed in an 8-pin TSOT-23 (TS8) surface-mount package. The part consumes only 0.5 mA from a single 2.35 V to 3.6 V supply, scales its supply current linearly with sample rate (Nap mode), and integrates a low-noise input structure that supports single-ended inputs with a 0 V to VDD or 0 V to VREF range. Per the LTC2360 family datasheet, the converter delivers true 12-bit performance with no missing codes and integral nonlinearity (INL) and differential nonlinearity (DNL) characterized for the commercial 0 °C to 70 °C temperature range. A SAR ADC is a type of analog-to-digital converter that uses a binary-search successive-approximation algorithm: each clock cycle the internal capacitive DAC is charged from the input and then iteratively switched against a reference to resolve one additional bit. SAR ADCs are valued for low latency (one conversion in N clocks), deterministic behavior, and excellent DC accuracy with no pipeline delay, making them the natural choice for multiplexed data-acquisition channels, industrial control loops, and precision instrumentation. The LTC2360 belongs to the broader ADC IC family (SAR -> ADC -> data converter -> signal chain -> analog IC) and is widely used where board area and power are constrained. Key features include 100 ksps sampling rate, single 3 V supply operation with 0.5 mA active supply current, automatic Nap-mode power-down that scales current with throughput, an external reference input for system-rail ratio-metric conversions, and a compact TSOT-23-8 footprint measuring roughly 2.9 mm x 1.6 mm. The device uses a simple SPI/QSPI/MICROWIRE-compatible serial interface, so it can communicate with virtually any microcontroller or DSP with as few as three digital lines. These traits let designers drop the part into densely populated PCBs without dedicated analog rails. The architecture combines a precision input sampling network, a charge-redistribution SAR core, and an internal conversion clock; the wide external-reference range (1 V to VDD) lets the dynamic range track the system reference rather than the supply, simplifying calibration in ratiometric designs. Nap mode and shutdown reduce IDD at low throughput, which is critical for battery-powered sensors that must idle most of the time and only wake for a quick burst of conversions. Typical applications include portable instrumentation, battery-powered sensor nodes, industrial process-control analog front ends, optical-module monitoring, and general-purpose data-acquisition boards. The TSOT-23 footprint is especially attractive for handheld medical devices and consumer audio accessories where PCB real estate is at a premium and the SPI interface simplifies integration with low-cost Cortex-M0 microcontrollers. When designing with this part, place the supply bypass capacitor (typically 10 µF tantalum in parallel with 0.1 µF ceramic) within a few millimeters of the VDD pin and route REF analog ground back to a single system star ground. Use short, symmetric analog traces to the analog input, and avoid running the serial clock near the analog input trace to prevent digital-to-analog coupling. This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes drawn from the LTC2360 family datasheet to provide practical context that is not always present on a single distributor listing.
LTC2360HTS8 - 12-Bit 100kSPS SAR ADC in TSOT-23-8 | Analog Devices
The Analog Devices LTC2360HTS8 is a 12-bit, 100 kSPS, single-channel, low-power successive-approximation-register (SAR) analog-to-digital converter that consumes only 0.5 mA from a single 3 V supply. Housed in a tiny TSOT-23-8 surface-mount package, the part delivers a serial SPI-compatible output and uses an external reference voltage, making it well suited to compact, power-constrained embedded designs. A SAR ADC is a sampling converter that uses a binary search through an internal capacitive DAC to resolve each analog sample in one conversion cycle. The SAR architecture offers a deterministic latency of one conversion cycle, intrinsic single-shot accuracy, and excellent dynamic performance at moderate sampling rates, distinguishing it from sigma-delta converters (which trade latency for higher resolution) and from pipeline ADCs (which require higher power and more complex calibration). Within the broader component hierarchy, the LTC2360HTS8 sits at: SAR ADC -> analog-to-digital converter -> data converter -> signal chain IC -> semiconductor. Key electrical features include 12-bit resolution, 100 kSPS maximum sampling rate, single-ended analog input, SPI/serial digital interface, external voltage reference, and 1:1 sample-and-hold-to-ADC ratio. Supply current scales down automatically at lower sampling rates, and the device operates from a 2.35 V to 3.6 V supply with a -40 °C to +125 °C extended automotive temperature range, making it a robust fit for industrial and harsh-environment data-acquisition front ends. Typical applications include portable instrumentation, sensor signal conditioning, isolated data acquisition, battery monitoring, and high-speed closed-loop control. The compact TSOT-23-8 footprint also enables use in space-constrained designs such as wearables, IoT edge nodes, and small-form-factor PLC analog input modules. When designing with this part, observe the analog input drive and reference decoupling recommendations in the manufacturer datasheet, and place the 0.1 µF reference bypass capacitor as close as possible to the REF pin to avoid conversion noise. The serial interface simplifies galvanic isolation and is compatible with most modern microcontrollers and DSPs. This page consolidates distributor pricing, drop-in alternatives in the same TSOT-23-8 footprint, and practical design considerations not found in a single datasheet excerpt, giving engineers a single reference for BOM validation, sourcing, and layout review.
LTC2360ITS8 - 12-bit 100ksps SAR ADC | Analog Devices | TSOT-23-8
The Analog Devices LTC2360ITS8 is a 12-bit, 100ksps successive-approximation-register (SAR) analog-to-digital converter (ADC) that draws only 0.5 mA from a single 3 V rail and is housed in a space-saving 8-pin TSOT-23 (TS8) package. Key headline parameters are 12-bit resolution, 100 ksamples per second conversion speed, and 0.5 mA typical supply current at full throughput. The device integrates an auto shutdown sequence between conversions, scaling supply current down to the nanoampere regime at reduced sampling rates, which makes it well suited to battery-powered and duty-cycled acquisition systems. A SAR ADC is a successive-approximation-register converter, a class of precision Nyquist-rate data converters that perform a binary search through an internal capacitive DAC using a single comparator and a logic SAR state machine. SAR is a sub-type of analog-to-digital converter (ADC), which itself belongs to the data-converter (or precision converter) family within the broader mixed-signal IC hierarchy. SAR ADCs are widely used for their deterministic latency, lack of pipeline delay, and excellent DC accuracy, making them a popular alternative to delta-sigma converters in multiplexed, multi-channel, and control-oriented applications. The LTC2360 family features a true-analog ground-referenced 0 V to VDD or 0 V to VREF unipolar input range, providing excellent ground-referenced signal handling for low-voltage sensors. The part operates from a single 2.7 V to 3.6 V analog supply, requires only 0.5 mA at 100 ksps, and supports an external reference up to VDD for designer-controlled input range scaling. Conversion is initiated through a simple serial-clock (SCK) protocol with a one-cycle latency, allowing direct interface to SPI-/QSPI-/MICROWIRE-compatible microcontrollers and DSPs without glue circuitry. Architecturally, the LTC2360ITS8 combines a precision low-power capacitive DAC, a high-speed comparator, and an internal oscillator. Auto shutdown between conversions drops quiescent current dramatically at lower sampling rates, allowing the part to consume microampere-level average current in duty-cycled sensor reads. Available in 6-pin and 8-pin TSOT-23 packages, the SOT-23 footprint enables extremely small board area, ideal for high-density sensor nodes, portable instrumentation, and space-constrained PCB layouts. Typical applications include portable and battery-powered sensor acquisition, isolated data acquisition front-ends, pen tablets and touch digitizers, consumer audio and instrumentation, industrial process control loops, and general-purpose analog monitoring. The wide operating range and small package also make it suitable for wearable health monitors and IoT edge devices. When designing with this part, ensure the reference pin is properly bypassed and that the analog input is bandwidth-limited to the 100 ksps Nyquist limit. The SOT-23-8 footprint with exposed pad requires careful PCB thermal layout to dissipate the modest power dissipation of approximately 1.5 mW at 100 ksps. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving engineers a single source for parametric, sourcing, and design-in information for the LTC2360ITS8.
LTC2361HTS8 - 250ksps 12-Bit SAR ADC | Analog Devices
The Analog Devices (formerly Linear Technology) LTC2361HTS8 is a 12-bit, 250 ksps, successive approximation register (SAR) analog-to-digital converter housed in a compact 8-pin TSOT-23 (HTS8) package. The device operates from a single 2.35 V to 3.6 V supply, drawing only 0.75 mA typical supply current at full sample rate, and supports a unipolar 0 V to VDD or 0 V to VREF input range with an external reference option for application flexibility. A SAR ADC is a type of data converter that uses a binary search algorithm and a capacitive DAC to digitize an analog input. SAR converters are valued for low latency (single-cycle conversion), deterministic behavior, and high dynamic performance at moderate sample rates. The LTC2361 belongs to the broader data converter (ADC) family, which sits within the signal chain hierarchy of analog mixed-signal ICs, ultimately serving precision measurement, industrial, and instrumentation systems. Key features of the LTC2361HTS8 include 12-bit resolution with no missing codes, an SPI/MICROWIRE-compatible serial interface, automatic power-down between conversions to reduce average current, and a small TSOT-23-8 footprint that enables high-density PCB designs. The LTC2360/LTC2361/LTC2362 family shares the same die and pinout across 100/250/500 ksps, allowing the same layout to be reused for different speed grades. The device accepts a 0 V to VDD or 0 V to VREF full-scale input, which suits single-ended sensor interfaces. The internal architecture combines a precision sample-and-hold front-end with a charge-redistribution SAR core, a high-bandwidth internal reference buffer, and on-chip conversion clock generation. The serial data output (SDO) and serial clock (SCK) use a simple three-wire interface that connects directly to microcontrollers, DSPs, and FPGAs, while the automatic nap mode between conversions reduces average power consumption at lower throughput rates. Typical applications for the LTC2361HTS8 include portable instrumentation, data acquisition front-ends, battery monitoring, industrial process control loops, and isolated sensor signal conditioning. The wide supply range and low current draw also make it suitable for low-power remote monitoring and energy-harvesting systems. When designing with the LTC2361HTS8, observe the input driving requirements in the manufacturer datasheet — the S/H front-end has specific acquisition-time and source-impedance constraints. A low-impedance buffer or op-amp driver is often required to reach the rated THD and SNR performance; a poor driver will noticeably degrade the converter's effective resolution. This page synthesizes distributor pricing, drop-in alternatives drawn from the LTC2360/2361/2362 same-package family, and practical design notes not found in the manufacturer datasheet, providing a one-stop engineering reference for selecting the LTC2361HTS8.
LTC2361ITS8 - 12-Bit 250ksps SAR ADC in TSOT-23 | Analog Devices
The Analog Devices LTC2361ITS8 is a 12-bit, 250 ksps successive-approximation analog-to-digital converter that operates from a single 2.7 V to 3.6 V supply and draws only 0.5 mA during conversion in a tiny 6-pin/8-pin TSOT-23 (MO-193) SMD package. It features a single-ended analog input, an external reference, a low-power auto-shutdown that drops supply current between conversions, and a high-speed SPI/serial interface compatible with 1.8 V logic. The device is a member of the pin-compatible LTC2360 (100 ksps), LTC2361 (250 ksps), and LTC2362 (500 ksps) family, allowing designers to scale throughput on a single PCB layout. What is a SAR ADC? A successive-approximation-register ADC is a topology that converts an analog input to a 12-bit digital code in one internal clock cycle by binary-searching a capacitive DAC against the sampled input voltage. SAR converters sit in the ADC hierarchy under Nyquist-rate data converters and above flash and dual-slope converters, offering an industry-standard balance of low power consumption, small footprint, and high accuracy for general-purpose data acquisition. Key features include true 12-bit performance with no missing codes, an external reference that sets input common-mode and full-scale range, a sample-and-hold front-end accepting 0 V to VREF inputs, and a serial data interface that reduces pin count versus parallel-output ADCs. Compared with the 100 ksps LTC2360, the LTC2361 doubles throughput for the same package and supply current, and the LTC2362 doubles throughput again. Technically, the architecture auto-powers-down between conversions and reduces supply current proportionally to the actual conversion rate; at 1 ksps the supply current falls well below 0.5 mA, yielding industry-leading sample-rate-to-power efficiency for battery-powered and remote-sensor applications. Typical applications include compact 12-bit data acquisition systems, portable instrumentation, sensor signal conditioning with microcontroller-based post-processing, loop-powered industrial 4-20 mA digitizers, and handheld medical monitoring where board area is constrained. When designing with the LTC2361ITS8, place the 0.1 uF decoupling capacitor close to the VDD pin and observe the tACQ acquisition-time timing budget to ensure rated linearity at full throughput. A clean low-noise VREF source is required for full 12-bit accuracy. This page synthesizes distributor pricing, verified pin-compatible alternatives in the TSOT-23 footprint, and practical design notes that go beyond a single datasheet summary.
LTC2362HTS8 - 12-Bit 500ksps SAR ADC TSOT-23-8 | Analog Devices
The Analog Devices LTC2362HTS8 is a 12-bit, 500 ksps successive approximation register (SAR) analog-to-digital converter housed in an 8-pin TSOT-23 (HTS8) package. It operates from a single 3 V supply and draws only 1.1 mA during conversion, automatically powering down between conversions to extend battery life. The full-scale analog input range is 0 V to VDD (or VREF), and the digital interface is a compact SPI/QSPI/MICROWIRE-compatible serial port that supports daisy-chaining of multiple ADCs. An ADC (analog-to-digital converter) is a data-conversion IC that translates a real-world analog voltage into a discrete digital code for processing by a microcontroller, DSP, or FPGA. SAR ADCs sample the input through a track-and-hold, perform a binary search against an internal DAC, and present the result one bit per clock cycle. In the broader hierarchy, the LTC2362HTS8 sits in the SAR-ADC family within the data-converter category of mixed-signal integrated circuits. The 12-bit resolution and 500 ksps throughput place it in the precision low-power tier favored for instrumentation, sensor read-out, and portable measurement front-ends. Key specifications include 12-bit resolution, 500 ksps sampling rate, 1.1 mA typical supply current at full speed, automatic nap/power-down between conversions, a single-ended 0 V to VDD input range, and a SPI-compatible serial interface. The HTS8 suffix designates the TSOT-23-8 surface-mount package with a thermal-pad-exposed lead frame that lowers thermal resistance versus a conventional SOT-23 footprint. Operating temperature range spans –40 °C to +125 °C (H grade), and the device is specified over the extended industrial range for harsh-environment designs. The 500 ksps sampling rate makes the LTC2362HTS8 well suited to multi-channel multiplexing architectures where each channel is sampled sequentially. The combination of low 1.1 mA supply current and automatic power-down enables battery-powered data-acquisition systems that idle most of the time and only burst-sample on demand. Designers should keep in mind that the H grade operating range, TSOT-23-8 footprint, and 3 V nominal supply set this part apart from higher-resolution or higher-speed pipeline ADCs in the broader product family. Typical applications include portable instrumentation, multi-channel data-acquisition front-ends, sensor signal conditioning read-outs, and industrial process-control analog input modules. This page synthesizes distributor stock, drop-in pin-compatible alternatives within the LTC236x family, and practical layout notes that complement the official datasheet.
LTC2362ITS8 - 500ksps 12-Bit Serial ADC | Analog Devices
The Analog Devices LTC2362ITS8 is a 500 ksps, 12-bit, sampling Successive Approximation Register (SAR) analog-to-digital converter that operates from a single 3V supply and draws only 1.1 mA. Housed in a compact TSOT-23-8 (TS) package, this ADC is part of the LTC2360/LTC2361/LTC2362 family, where the -2 suffix variant delivers the highest sample rate of the trio. A single-ended analog input is sampled through a low-noise front end, and conversions are clocked via an external SCK, with results shifted out through a simple SPI-compatible serial interface. A SAR ADC is a successive-approximation-register analog-to-digital converter that uses a binary search across an internal capacitive DAC to resolve each conversion in N clock cycles. SAR ADCs offer deterministic latency, no pipeline delay, and excellent DC accuracy, which makes them the architecture of choice for multiplexed data-acquisition systems, industrial sensor front-ends, and precision instrumentation where every sample's timing relationship to the input must be exact. Key features of the LTC2362ITS8 include 12-bit resolution, 500 ksps throughput, an integrated low-drift reference, 1.1 mA typical supply current at full speed, automatic power-down between conversions to reduce average current, and a wide input common-mode range. The TSOT-23-8 footprint is roughly half the board area of an MSOP-10, making this part attractive for space-constrained designs. The supply current drops automatically at lower sample rates, supporting battery-powered applications without sacrificing dynamic performance. Architecturally, the device combines a sample-and-hold amplifier, a charge-redistribution DAC, a comparator, and a SAR control state machine. The 3-wire serial interface (CS, SCK, SDO) is compatible with standard SPI and Microwire controllers, requiring no external configuration registers - the part is hardware-strapped for 12-bit mode at 500 ksps. Internal calibration on power-up trims offset and linearity, simplifying software bring-up. Typical applications include portable instrumentation, battery-powered data loggers, isolated industrial sensor front-ends, and general-purpose multi-channel analog monitoring where the SPI output feeds a microcontroller or FPGA. The combination of high speed, small package, and low current also suits handheld medical sensors and 4-20 mA loop-powered smart transmitters. When designing with the LTC2362ITS8, place a 0.1 uF decoupling capacitor within 2 mm of the VDD pin and keep the analog input traces short and guarded. The reference is internal, so an external bypass of 1 uF is recommended. Ensure the SPI SCK frequency does not exceed the device's maximum to maintain conversion accuracy at full throughput. This page synthesizes real-time distributor pricing, drop-in compatible same-family variants, and practical PCB-level design guidance not found in the manufacturer datasheet alone.
LTC2365CTS8 - 12-bit 1Msps SAR ADC | Analog Devices
The Analog Devices LTC2365CTS8 is a 12-bit, 1 Msps, single-ply sampled successive-approximation analog-to-digital converter (SAR ADC) housed in an 8-pin TSOT-23 package. Operating from a single 3 V supply, the device consumes only 2 mA during conversion, making it suitable for power-constrained and portable designs. The LTC2365 accepts a unipolar analog input range of 0 V to VDD or 0 V to VREF and delivers 72 dB SINAD and -80 dB THD at full speed, supporting precision measurement front-ends. An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous analog voltages into binary digital words; the SAR (Successive Approximation Register) architecture is one of the most widely used ADC topologies, valued for its deterministic latency, low power, and ability to deliver medium-to-high resolution at multi-Msample/s rates. Within the broader hierarchy, the LTC2365 sits in the SAR ADC -> data converter -> mixed-signal IC -> semiconductor family, sharing this category with 12-, 14-, and 16-bit precision converters from Analog Devices, Texas Instruments, and Maxim. Key features of the LTC2365CTS8 include a high dynamic range sample-and-hold circuit, a high-speed serial SPI-compatible interface, 2 mA typical supply current, and the industry's smallest footprint for a 12-bit 1 Msps ADC - the 8-lead TSOT-23 surface-mount package measuring only 2.9 mm × 2.8 mm. These characteristics are engineered for space-limited, low-power precision applications such as instrumentation front-ends, sensor signal chains, and portable data-acquisition systems. The LTC2365CTS8 employs a charge-redistribution SAR core with an integrated sample-and-hold amplifier. Conversion is initiated on the falling edge of CONVST and the result is clocked out via a serial interface (SCK and SDO), enabling direct connection to most microcontrollers, DSPs, or FPGAs without glue logic. Internal reference buffering simplifies external BOM. Typical applications include industrial process control loops, portable medical instrumentation, automotive sensor interfaces, optical module monitoring, multichannel data-acquisition cards, and isolated ADC front-ends driven by digital isolators. When designing with this device, pay close attention to PCB layout: keep analog and digital grounds separated, decouple VDD close to the IC with a 0.1 uF ceramic capacitor, and treat the REF pin carefully to avoid injection of digital switching noise. The TSOT-23 package has low thermal mass, so avoid sustained sampling at the absolute maximum ratings without adequate PCB copper area. This page synthesizes distributor pricing, drop-in TSOT-23 alternatives, and practical design notes not found in the manufacturer datasheet alone.
LTC2365HTS8 - 12-Bit 1Msps SAR ADC | Analog Devices | TSOT-23-8
The Linear Technology/Analog Devices LTC2365HTS8 is a 12-bit, 1Msps successive-approximation analog-to-digital converter (SAR ADC) packaged in an 8-pin TSOT-23 (TS8) and drawing only 2 mA from a single 2.5 V or 3 V supply. Background: A SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is a class of data converter that performs a binary search across the analog input range using an internal DAC and comparator, producing one conversion per N clock cycles for N bits of resolution. SAR ADCs sit within the broader ADC family (SAR, sigma-delta, pipeline, flash) and are widely chosen for applications that need deterministic latency, low power, and small package size. The LTC2365 belongs to the TSOT-23 ADC family from Analog Devices, optimized for space-constrained precision front ends. Key features include a high dynamic range sample-and-hold front end, a high-speed SPI-/QSPI-/MICROWIRE-compatible serial interface, an external reference option (0 V to VDD or 0 V to VREF input range), 72 dB SINAD and -80 dB THD at full sample rate, and a 1 Msps throughput in the LTC2365 grade. The low 2 mA supply current at 1 Msps makes the part suitable for battery-powered and portable instruments, while the TSOT-23-8 footprint allows placement directly next to sensors on crowded mixed-signal boards. Architecturally, the device pairs a charge-redistribution capacitive DAC with an internal oscillator and clock generator; no external clock source is required, which simplifies BOM. The high-impedance analog input and reference pin allow direct connection to low-power sensor outputs or to a precision external reference such as the LT1461. Nap and shutdown modes further reduce current consumption to microampere levels for duty-cycled measurements. Typical applications include portable data acquisition, multichannel sensor front-end digitization, isolated or industrial process control loops, optical module monitoring, and instrumentation where a small serial ADC saves board area. The wide input common-mode range and small 3 mm x 2.9 mm TSOT-23 footprint make it ideal for high-density plug-in modules where SPI-based ADCs are preferred over parallel-interface devices. When designing with the LTC2365, place a 0.1 uF decoupling capacitor as close as possible to the VDD pin, route the analog input traces away from the serial clock, and use a low-noise reference if DC accuracy below 1 LSB is needed at 12 bits. The LTC2365HTS8 is one of several H-grade speed variants; the C-, I-, and H-suffix parts differ in throughput (200 ksps / 500 ksps / 1 Msps respectively), allowing designers to scale speed and power with the same PCB layout. This page synthesizes distributor pricing, drop-in same-family variants, and practical design notes not all found in a single manufacturer data brief.