EP1810GC-35AB vs EP1810GC-35 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810GC-35AB disebabkan oleh Altera dan EP1810GC-35 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester
EP1810GC-35 ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EP1810GC-35AB | EP1810GC-35 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Masa Terakhir Dibeli |
| Product Family | Classic EPLD | — |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM cells |
| Number of Macrocells | 48 | — |
| Number of Usable Gates | 1200 | — |
| Maximum Inputs | 64 | 64 |
| Maximum Outputs | 48 | 48 |
| Number of I/O Pins | 48 | — |
| Dedicated Input Pins | 12 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | Pin Grid Array (PGA), ceramic | — |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Programming Method | UV-erasable EPROM, in-system via JTAG-like interface | UV erasure + EPROM programming |
| Status RoHS | unknown | Not applicable (legacy ceramic package) |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Family | — | Altera Classic EPLD |
| Kemasan | — | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| Bilangan Pin | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Macrocells | — | 16 |
| I/O Standard | — | TTL-compatible |
| Tegangan Pemberi Arus | — | [DATA_NEEDED: VCC range] |
| Jenis Pemasangan | — | Through Hole |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |