EP1810GM883 vs EP1810GC-35AB Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810GM883 disebabkan oleh Altera dan EP1810GC-35AB disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP1810GM883 EP1810GC-35AB
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family Classic EPLD (EP1810 series) —
Device Type UV-Erasable Programmable Logic Device (EPLD) —
Macrocells 48 —
Dedicated Inputs 12 —
User I/O Pins 48 —
Total Terminals 68 —
Global Clocks 4 —
Supply Voltage (Vcc) 4.5 V to 5.5 V (nominal 5 V) —
Propagation Delay (tpd) 45 ns (max) —
Maximum Toggle Frequency (fmax) [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] —
Process Technology CMOS, UV-erasable —
Kemasan 68-Pin Ceramic Pin Grid Array (PGA) —
Suhu Operasi -55C to +125C (MIL-STD-883 Class B) [DATA_NEEDED: operating temperature range]
Screening MIL-STD-883 Class B (suffix '883' denotes MIL processing) —
Jenis Pemasangan Through-Hole (PGA socket) —
Status RoHS [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] unknown
Lead-Free [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] —
Product Family — Classic EPLD
Technology — CMOS EPROM
Number of Macrocells — 48
Number of Usable Gates — 1200
Maximum Inputs — 64
Maximum Outputs — 48
Number of I/O Pins — 48
Dedicated Input Pins — 12
Propagation Delay (tPD) — 35 ns
Maximum Toggle Frequency — 62.5 MHz
Supply Voltage (VCC) — 5 V
Package Type — Pin Grid Array (PGA), ceramic
Programming Method — UV-erasable EPROM, in-system via JTAG-like interface

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