EP1K100FC256-2 vs EP1K100FI256-3 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1K100FC256-2 disebabkan oleh Altera dan EP1K100FI256-3 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Intel
EP1K100FI256-3 - 100K-Gate ACEX 1K FPGA, 186 I/O, FBGA-256 | Intel
EP1K100FI256-3 ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EP1K100FC256-2 | EP1K100FI256-3 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Masa Terakhir Dibeli |
| Product Family | ACEX-1K | — |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Equivalent Logic Gates | 257000 | — |
| Logic Elements / Cells | 4992 | — |
| Logic Array Blocks (LABs) | 624 | — |
| Total RAM Bits | 49152 | — |
| User I/O Pins | 186 | 186 |
| Core Supply Voltage | 2.5 V | — |
| Technology | 0.22 um CMOS | — |
| Kemasan | 256-Ball FBGA (256-BGA) | 256-ball FineLine BGA (FBGA-256) |
| Number of Terminals | 256 | — |
| Terminal Form | Ball | — |
| Terminal Pitch | 1.00 mm | — |
| Package Shape | Square | — |
| Speed Grade | -2 | -3 |
| Maximum Internal Frequency | 250 MHz | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Operating Temperature Grade | Commercial (C suffix); exact min/max [DATA_NEEDED: Operating temperature range] | — |
| Family | — | ACEX 1K |
| Device Logic Elements | — | 4,992 |
| Typical Gate Count | — | 100,000 gates |
| Maximum RAM Bits | — | 49,152 bits |
| Dedicated Inputs | — | 6 |
| Nominal Core Voltage | — | 2.5 V |
| Core Voltage Range | — | 2.375 V to 2.625 V |
| Process Technology | — | 0.22 micron CMOS |
| Gambaran Suhu Operasi | — | -40 C to +85 C (Industrial) |
| Configuration Method | — | SRAM-based, JTAG / PS / AS supported |
| Status RoHS | — | [DATA_NEEDED: RoHS status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| AEC-Q100 Qualification | — | Not qualified |
| Aras MSL | — | [DATA_NEEDED: MSL level] |
| JTAG Boundary Scan | — | Yes (IEEE 1149.1) |