EP1SGX25FF1020C7 vs EP1SGX25FF1020I7 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1SGX25FF1020C7 disebabkan oleh Altera dan EP1SGX25FF1020I7 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EP1SGX25FF1020C7 - 25K LE Stratix GX FPGA, 607 I/O, 1020-FBGA | Altera
EP1SGX25FF1020C7 ObsoleteAltera
EP1SGX25FF1020I7 - Stratix GX FPGA 25,660 Cells, 1.5V, FC-FBGA-1020 | Altera / Intel
EP1SGX25FF1020I7 ObsoletePengandingan Spesifikasi
| Parametr | EP1SGX25FF1020C7 | EP1SGX25FF1020I7 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | Stratix GX | Stratix GX |
| Logic Elements | 25,660 | — |
| Number of LABs/CLBs | 2,566 | — |
| Total RAM Bits | 1,944,576 | — |
| User I/O Count | 607 | — |
| Number of Gates | [DATA_NEEDED: gate count not provided in source data] | — |
| Supply Voltage - Core | 1.425 V to 1.575 V | — |
| Jenis Pemasangan | Surface Mount | Surface Mount (FC-FBGA) |
| Kemasan / Case | 1020-BBGA, FCBGA (33 x 33 mm, 1 mm pitch) | — |
| Supplier Device Package | 1020-FBGA (33x33) | — |
| Logic Family | CMOS | — |
| Suhu Operasi | 0 C to 85 C | — |
| Lead Free | Yes (per digchip datasheet) | — |
| Status RoHS | [DATA_NEEDED: not stated in source data] | [DATA_NEEDED: RoHS compliance] |
| Max Operating Frequency (cited) | 4385.97 MHz (per Arrow listing) | — |
| Process Technology | 1.5 V CMOS | 130 nm CMOS |
| Series | — | EP1SGX25 |
| Logic Cells | — | 25,660 |
| Configurable Logic Blocks (CLBs) | — | 2,566 |
| Core Supply Voltage | — | 1.5 V |
| Kemasan | — | FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) |
| Number of Terminals / Balls | — | 1020 |
| Terminal Form | — | Ball |
| Temperature Grade (suffix 'I') | — | Industrial |
| Speed Grade | — | 7 (highest production grade) |
| Terminal Pitch | — | [DATA_NEEDED: terminal pitch] |
| Combinatorial Delay per CLB | — | 9.48 ns (per Microchip USA listing) |
| Combinatorial Delay Variant | — | [DATA_NEEDED: tPD per CLB variant speed grade] |
| Maximum Internal Clock Frequency | — | [DATA_NEEDED: max Fmax in MHz per speed grade] |
| Embedded Transceivers | — | Yes (Stratix GX feature) |
| Configuration Method | — | SRAM-based (volatile, requires configuration at power-up) |
| Aras MSL | — | [DATA_NEEDED: MSL level] |