EP20K100EBC356-3N vs EP20K200EBC356-2 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K100EBC356-3N disebabkan oleh Altera dan EP20K200EBC356-2 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP20K100EBC356-3N | EP20K200EBC356-2 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Series | APEX-20KE | APEX 20KE |
| Family | APEX 20K | APEX 20K (APEX 20KE enhancement) |
| Logic Elements / Cells | 4160 | — |
| System Gates | 100,000 | — |
| Embedded Memory (bits) | 53,248 | — |
| Embedded System Blocks (ESBs) | 26 | — |
| Maximum User I/Os | 246 | — |
| Bilangan Pin | 356 | — |
| Kemasan | 356-LBGA (Ball Grid Array) | — |
| Package Dimensions | 45 x 45 mm | — |
| Ball Pitch | 1.27 mm | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 1.8 V | — |
| Propagation Delay | 1.6 ns (speed grade -3N) | 2.5 ns |
| Maximum Internal Frequency | 250 MHz | — |
| Suhu Operasi | 0 °C to +85 °C | 0 C to 85 C (commercial) |
| Jenis Pemasangan | Surface Mount | Surface Mount (BGA) |
| Programmable Interface | JTAG (IEEE 1149.1) | — |
| I/O Standards Supported | LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+ | — |
| Status RoHS | [DATA_NEEDED: rohs_status] | — |
| Typical Gates | — | 200,000 |
| Maximum Logic Elements | — | 8320 |
| Macros / Logic Cells | — | 832 |
| Maximum Flip-Flops | — | 13,824 |
| Embedded RAM | — | 53,248 bits |
| User I/Os | — | 271 |
| Number of Terminals / Pins | — | 356 (LBGA) |
| Tegangan Pemberi Arus | — | 2.5 V (core) |
| Logic Family | — | CMOS |
| Number of PLLs | — | 4 embedded PLLs |
| Number of DDR Interfaces | — | 4 |
| Package Type | — | 356-LBGA (EBC suffix) |
| Speed Grade | — | -2 |
| Compliance | — | RoHS status [DATA_NEEDED: RoHS] |