EP20K400CF672C-7ES vs EP20K400CF672C-8 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K400CF672C-7ES disebabkan oleh Altera dan EP20K400CF672C-8 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EP20K400CF672C-7ES - 400K Gates APEX 20KC FPGA | Altera | 672-BGA
EP20K400CF672C-7ES ObsoletePengandingan Spesifikasi
| Parametr | EP20K400CF672C-7ES | EP20K400CF672C-8 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20K |
| Series | EP20K400 | — |
| System Gates | 400,000 | — |
| Logic Elements | 16,640 | 16,640 |
| Embedded Memory (bits) | 212,992 | — |
| Maximum User I/O | 488 | 488 |
| Number of PLLs | 4 | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count from datasheet] | — |
| Process Technology | 0.15 um CMOS | 0.15 µm all-layer copper CMOS |
| Core Voltage | 1.8 V | — |
| Speed Grade | -7 | -8 |
| Maximum Internal Clock Frequency | 375.94 MHz | — |
| Propagation Delay (per Sierra IC) | 1.400 ns | — |
| Gambaran Suhu Operasi | 0 C to 85 C (commercial) | — |
| Kemasan | 672-BGA (FineLine BGA, 1.00 mm pitch) | — |
| Jenis Pemasangan | Surface Mount | Surface Mount (BGA) |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Configuration Support | EPC16, EPC8, EPC4, EPC2, EPC1 serial devices; JTAG | — |
| Typical Gates | — | 400,000 |
| Macros | — | 1,664 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Package Type | — | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO options] |
| Pin-to-Pin Delay (tPD) | — | 1.78 ns (speed grade -8) |
| Temperature Grade (C) | — | Commercial, 0 °C to 85 °C |
| Embedded Memory Type | — | ESB (RAM / ROM / CAM) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Aras MSL | — | [DATA_NEEDED: MSL level] |