EP20K400CF672I8 vs EP20K400CF672I9 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K400CF672I8 disebabkan oleh Intel dan EP20K400CF672I9 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP20K400CF672I8 | EP20K400CF672I9 |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Series | EP20K400 | — |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 | 400,000 |
| Embedded Memory (RAM bits) | 212,992 | — |
| Number of Logic Macros | 1664 | — |
| User I/O Pins | 488 | — |
| Supply Voltage - Core | 1.8 V | — |
| I/O Voltage (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Maximum Internal Frequency | 301.21 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Speed Grade | I8 | I9 (Industrial) |
| Package Type | 672-pin FC-FBGA (FineLine BGA) | — |
| Operating Temperature (Industrial) | -40 °C to +100 °C | — |
| Jenis Pemasangan | Surface Mount (BGA) | — |
| Configuration Method | Passive Serial / Active Serial / JTAG (IEEE 1149.1) | — |
| PLLs | 4 | — |
| Aras MSL | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (e0 terminal finish indicates SnPb) |
| Logic Elements | — | 16,640 cells |
| Maximum Operating Frequency | — | 250 MHz |
| Embedded RAM | — | 212,992 bits |
| Embedded System Blocks (ESBs) | — | 104 |
| Maximum User I/O Pins | — | [DATA_NEEDED: max user I/O count] |
| Core Voltage | — | 1.8 V |
| I/O Voltage | — | 1.8 V / 3.3 V (MultiVolt) |
| Kemasan | — | 672-ball FC-FBGA (FineLine BGA) |
| Package Pitch | — | 1.0 mm |
| Suhu Operasi | — | -40°C to +85°C (Industrial) |
| Tingkat sensitiviti Air Nama (MSL) | — | 3 |
| Terminal Finish | — | e0 (Tin-Lead, per JESD-609) |