EP20K400CF672I8 vs EP20K400CF672I9 Karşılaştırma
Ayrıntılı yan yana karşılaştırma EP20K400CF672I8 tarafından Intel ve EP20K400CF672I9 tarafından IntelAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.
Özellik Karşılaştırması
| Parametre | EP20K400CF672I8 | EP20K400CF672I9 |
|---|---|---|
| Marka | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Yaşam Döngüsü Durumu | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Series | EP20K400 | — |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 | 400,000 |
| Embedded Memory (RAM bits) | 212,992 | — |
| Number of Logic Macros | 1664 | — |
| User I/O Pins | 488 | — |
| Supply Voltage - Core | 1.8 V | — |
| I/O Voltage (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Maximum Internal Frequency | 301.21 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Speed Grade | I8 | I9 (Industrial) |
| Package Type | 672-pin FC-FBGA (FineLine BGA) | — |
| Operating Temperature (Industrial) | -40 °C to +100 °C | — |
| Montaj Türü | Surface Mount (BGA) | — |
| Configuration Method | Passive Serial / Active Serial / JTAG (IEEE 1149.1) | — |
| PLLs | 4 | — |
| MSL Seviyesi | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| RoHS Durumu | [DATA_NEEDED: RoHS compliance] | Non-compliant (e0 terminal finish indicates SnPb) |
| Logic Elements | — | 16,640 cells |
| Maximum Operating Frequency | — | 250 MHz |
| Embedded RAM | — | 212,992 bits |
| Embedded System Blocks (ESBs) | — | 104 |
| Maximum User I/O Pins | — | [DATA_NEEDED: max user I/O count] |
| Core Voltage | — | 1.8 V |
| I/O Voltage | — | 1.8 V / 3.3 V (MultiVolt) |
| Paket | — | 672-ball FC-FBGA (FineLine BGA) |
| Package Pitch | — | 1.0 mm |
| İşletim Sıcaklığı | — | -40°C to +85°C (Industrial) |
| Nem Hassasiyet Seviyesi (MSL) | — | 3 |
| Terminal Finish | — | e0 (Tin-Lead, per JESD-609) |