EP20K600CB652C9 vs EP20K600CB652C7ES Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K600CB652C9 disebabkan oleh Altera dan EP20K600CB652C7ES disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP20K600CB652C9 EP20K600CB652C7ES
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family APEX 20KC APEX 20KC
Logic Elements / Cells 24,320 —
Number of LABs / CLBs 2,432 —
System Gates 1,537,000 600,000
Total RAM Bits 311,296 —
User I/O 488 —
Number of I/O Banks [DATA_NEEDED: I/O bank count] —
Tegangan Pemberi Arus 1.71 V to 1.89 V —
Process Technology 0.15 µm all-layer copper CMOS 0.15 µm CMOS
Internal Datapath Frequency up to 250 MHz —
Propagation Delay (typ.) 1.48 ns —
Suhu Operasi 0 °C to 85 °C (commercial) 0 °C to +85 °C (commercial)
Kemasan 652-BGA (45 × 45 mm, 1.27 mm pitch) —
Jenis Pemasangan Surface Mount (BGA) Surface Mount (BGA)
Configuration JTAG IEEE 1149.1 / serial / EPC2-compatible —
Status RoHS Compliant (per Altera product page) [DATA_NEEDED: RoHS status]
Product Status Obsolete (per distributor listings) —
Logic Elements — 24,320
Maximum System Gates — 1,053,840
Embedded Memory Bits — 311,296
Embedded System Blocks (ESB) — 26
Maximum User I/O — 488
User I/O (this package) — 488 (652-BGA)
Supply Voltage - Core — 1.71 V to 1.89 V (1.8 V nominal)
Maximum Internal Clock Frequency — 1666.6 MHz
Propagation Delay — 1.6 ns
Package Type — 652-ball FineLine BGA
JEDEC Package Code — S-PBGA-B652
Configuration Modes — Passive Serial, Passive Parallel, JTAG
JTAG Boundary Scan — IEEE 1149.1 compliant
PLLs — 4

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