EP20K600CB652I7 vs EP20K600CB652C7ES Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K600CB652I7 disebabkan oleh Intel dan EP20K600CB652C7ES disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP20K600CB652I7 EP20K600CB652C7ES
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family APEX 20KC APEX 20KC
Manufacturer Intel (formerly Altera) —
Technology 0.15 µm CMOS, SRAM-based —
System Gates 600,000 600,000
Logic Elements 24,320 24,320
Maximum Internal Frequency 375.94 MHz —
Propagation Delay 1.6 ns 1.6 ns
Core Supply Voltage 1.8 V (1.71 V to 1.89 V range) —
User I/O Count 488 (4 dedicated inputs + 480 I/O) —
Bilangan Output 480 —
Kemasan 652-ball FineLine BGA (LBGA, 1.27 mm pitch) —
Jenis Pemasangan Surface Mount Surface Mount (BGA)
Suhu Operasi -40 °C to +85 °C (industrial, 'I' suffix) 0 °C to +85 °C (commercial)
Speed Grade -7 —
Programming Interface JTAG (IEEE 1149.1), in-system programmable —
Embedded Memory ESBs configurable as dual-port RAM / ROM / CAM —
MultiVolt I/O Support 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant banks —
Status RoHS unknown [DATA_NEEDED: RoHS status]
Maximum System Gates — 1,053,840
Embedded Memory Bits — 311,296
Embedded System Blocks (ESB) — 26
Maximum User I/O — 488
User I/O (this package) — 488 (652-BGA)
Supply Voltage - Core — 1.71 V to 1.89 V (1.8 V nominal)
Maximum Internal Clock Frequency — 1666.6 MHz
Process Technology — 0.15 µm CMOS
Package Type — 652-ball FineLine BGA
JEDEC Package Code — S-PBGA-B652
Configuration Modes — Passive Serial, Passive Parallel, JTAG
JTAG Boundary Scan — IEEE 1149.1 compliant
PLLs — 4

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