EP20K600CB652I7 vs EP20K600CB652C7ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB652I7 sa pamamagitan ng Intel at EP20K600CB652C7ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600CB652I7 | EP20K600CB652C7ES |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Manufacturer | Intel (formerly Altera) | — |
| Technology | 0.15 µm CMOS, SRAM-based | — |
| System Gates | 600,000 | 600,000 |
| Logic Elements | 24,320 | 24,320 |
| Maximum Internal Frequency | 375.94 MHz | — |
| Propagation Delay | 1.6 ns | 1.6 ns |
| Core Supply Voltage | 1.8 V (1.71 V to 1.89 V range) | — |
| User I/O Count | 488 (4 dedicated inputs + 480 I/O) | — |
| Bilang ng Outputs | 480 | — |
| Packhaging | 652-ball FineLine BGA (LBGA, 1.27 mm pitch) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Temperature na Operasyon | -40 °C to +85 °C (industrial, 'I' suffix) | 0 °C to +85 °C (commercial) |
| Speed Grade | -7 | — |
| Programming Interface | JTAG (IEEE 1149.1), in-system programmable | — |
| Embedded Memory | ESBs configurable as dual-port RAM / ROM / CAM | — |
| MultiVolt I/O Support | 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant banks | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Maximum System Gates | — | 1,053,840 |
| Embedded Memory Bits | — | 311,296 |
| Embedded System Blocks (ESB) | — | 26 |
| Maximum User I/O | — | 488 |
| User I/O (this package) | — | 488 (652-BGA) |
| Supply Voltage - Core | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Maximum Internal Clock Frequency | — | 1666.6 MHz |
| Process Technology | — | 0.15 µm CMOS |
| Package Type | — | 652-ball FineLine BGA |
| JEDEC Package Code | — | S-PBGA-B652 |
| Configuration Modes | — | Passive Serial, Passive Parallel, JTAG |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| PLLs | — | 4 |