EP20K600CF672I8AA vs EP20K600CF672C8N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K600CF672I8AA disebabkan oleh Intel dan EP20K600CF672C8N disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Intel
EP20K600CF672I8AA - APEX 20KC 600K Gate FPGA | Intel
EP20K600CF672I8AA ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EP20K600CF672I8AA | EP20K600CF672C8N |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Aktif |
| Series | APEX 20KC | — |
| Logic Elements / Cells | 24,320 | — |
| Total Gates | 600,000 (system gates) | — |
| Total RAM Bits | 311,296 | — |
| Number of I/O | 508 | — |
| Number of LABs/CLBs | 1,520 | — |
| Tegangan Pemberi Arus | 1.71 V to 1.89 V | 1.8 V |
| Jenis Pemasangan | Surface Mount | Surface mount |
| Kemasan | 672-FBGA (27 x 27 mm) | BGA-652, 45 x 45 mm, 1.27 mm pitch |
| Suhu Operasi | -40C to +85C (industrial) | 0°C to 85°C |
| Technology | 0.15 um CMOS | — |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL, SSTL-2/3, HSTL, LVDS, LVPECL | — |
| Number of PLLs | 4 | — |
| Speed Grade | I8 | — |
| Status RoHS | Compliant | unknown |
| Lead Free | Yes | — |
| Number of Logic Array Blocks | 1,520 (40 LABs per MegaLAB) | — |
| Device Type | — | SPLD |
| Product Type | — | FPGA / programmable logic device |
| Family | — | APEX 20KC |
| Nominal Gate Capacity | — | 600K gates |
| Logic Elements or Cells | — | 24,320 |
| Macros | — | 2,432 |
| User I/O Count | — | 508 |
| Package Terminals | — | 652 pins |
| Package Description | — | 672-pin FC-FBGA |
| Listed Frequency | — | 301.21 MHz |
| Propagation Delay | — | 1.48 ns |
| Fabrication Process | — | 0.15 µm |
| Interconnect Metal | — | All-layer copper metal |
| I/O Configuration | — | 508 user I/O |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |
| Configuration Method | — | [DATA_NEEDED: configuration memory and programming method] |
| Core Current | — | [DATA_NEEDED: core supply current] |
| I/O Bank Voltage | — | [DATA_NEEDED: supported I/O voltage range] |
| Junction Temperature | — | [DATA_NEEDED: maximum junction temperature] |
| Tegangan Panas | — | [DATA_NEEDED: junction-to-ambient thermal resistance] |