EP20K60EFC144-1 vs EP20K30EFC144-2X Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K60EFC144-1 disebabkan oleh Altera dan EP20K30EFC144-2X disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EP20K30EFC144-2X EP20K30EFC144-2X - 30K Gate APEX 20K FPGA | Altera

EP20K30EFC144-2X - 30K Gate APEX 20K FPGA | Altera

EP20K30EFC144-2X Obsolete

Pengandingan Spesifikasi

Parametr EP20K60EFC144-1 EP20K30EFC144-2X
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Device Family APEX 20KE Altera APEX 20K
Series APEX 20K —
Logic Family CMOS —
Typical Gates 60,000 30,000 gates
Maximum System Gates 256,000 —
Macrocells 256 —
Maximum User I/Os 93 (per datasheet; 196 max in 144-FBGA family datasheet) —
Embedded Memory 32,768 bits (2560 RAM blocks) —
Maximum Internal Frequency 160 MHz —
Propagation Delay 1.72 ns —
Core Supply Voltage 1.8 V 1.8 V
Speed Grade -1 -2X
Suhu Operasi 0 C to 85 C (Commercial) —
Kemasan 144-FBGA (Fine-pitch BGA) —
Package Pin Count 144 balls —
Jenis Pemasangan Surface Mount Surface Mount
Status RoHS [DATA_NEEDED: rohs_status] unknown
Programming Interface JTAG / ByteBlaster / Altera Programming Unit —
Device Type — Loadable programmable logic device (FPGA/CPLD hybrid)
Number of Logic Elements / Cells — 1,200 cells (third-party parametric listing)
Number of Macrocells — 192
Number of User I/O — 93
Number of Terminals — 144
Terminal Form — Ball
Package Code — LBGA / 144-FBGA
Package Shape — Square
Process Technology — 0.22 um
Gambaran Suhu Operasi — [DATA_NEEDED: exact operating temperature range]
Embedded RAM Bits — [DATA_NEEDED: embedded memory size]
Supported I/O Standards — [DATA_NEEDED: supported I/O standards]
Configuration Schemes — [DATA_NEEDED: supported configuration schemes]

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