EP610DC-35 vs EP610DC15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610DC-35 disebabkan oleh Altera dan EP610DC15 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP610DC-35 | EP610DC15 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | NRND |
| Device Type | CPLD - Classic EPLD | — |
| Family | Altera Classic EP610 | EP610 Classic EPLD |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 15 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Process Technology | CMOS | — |
| Program/erase Method | UV-erasable (windowed CERDIP) | — |
| Kemasan | 24-pin CDIP (windowed CERDIP) 0.300 inch | 24-pin CDIP (Ceramic DIP, windowed) |
| Jenis Pemasangan | Through-Hole (DIP) | Through-Hole |
| Suhu Operasi | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | 0C to +70C |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | — |
| Status RoHS | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | unknown |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Architecture | — | PAL-type |
| Maximum Clock Frequency (fMAX) | — | 71.4 MHz |
| Total Inputs | — | 20 |
| I/O Lines | — | 16 |
| Product Terms | — | 160 |
| Technology | — | CMOS |
| Reprogrammability | — | Yes (UV erasable via windowed package) |