EP610ILC-25 vs EP610IPC-25 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610ILC-25 disebabkan oleh Altera dan EP610IPC-25 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP610ILC-25 | EP610IPC-25 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Family | Classic EPLD (EP610 series) | Classic EPLD (EP610) |
| Device Type | EEPLD (Electrically Erasable PLD) | — |
| Usable Gates | 300 | — |
| Macrocells | 16 | — |
| Product Terms | 160 | 160 |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | — |
| Bidirectional I/O Pins | 16 | — |
| Gambaran Suhu Operasi | 0 C to +70 C (commercial) | — |
| Kemasan | 28-pin PLCC (J-lead) | 24-pin PDIP (Plastic DIP) |
| Jenis Pemasangan | Surface Mount | Through-Hole |
| Process Technology | CMOS, electrically erasable | — |
| Programming Method | In-system, electrically erasable | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (contains Pb, PDIP package) |
| Architecture | — | PAL-type, CMOS, Erasable |
| Propagation Delay (tpd) | — | 25 ns (max) |
| Maximum Inputs | — | 20 |
| Maximum I/O Pins | — | 16 |
| Dedicated Outputs | — | 16 |
| Suhu Operasi | — | 0 °C to +70 °C (Commercial) |
| Technology | — | CMOS, UV-erasable (windowless in IPC pkg) |
| TTL Compatibility | — | 100% TTL emulation |
| Aras MSL | — | [DATA_NEEDED: MSL level] |
| Logic Capacity | — | Equivalent to ~24 standard 24-pin PALs |