EP610PC-30 vs EP610PC-15 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610PC-30 disebabkan oleh Altera dan EP610PC-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP610PC-30 EP610PC-15
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND NRND
Device Family Classic EPLD (EP610) —
Macrocells 16 16
Usable Gates 300 300 gates
Propagation Delay (tPD) 30 ns —
Maximum Pipeline Frequency 33.3 MHz (typical) / 100 MHz pipelined —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 5 V (single supply)
Process Technology CMOS EPROM —
Kemasan 24-pin PDIP (0.300 inch) PDIP-24 (plastic DIP, 24-pin)
Jenis Pemasangan Through-Hole Through-Hole (DIP)
Programmability One-Time Programmable (OTP, no window on plastic PDIP) —
Suhu Operasi 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
Output Drive Current [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] —
Input Pins (Dedicated) [DATA_NEEDED: dedicated input count from datasheet pinout] —
I/O Pins [DATA_NEEDED: bidirectional I/O count from datasheet pinout] —
Programming Tool Altera A+PLUS / MAX+PLUS II (legacy) —
Status RoHS Not applicable (legacy non-compliant package per distributor listing) [DATA_NEEDED: RoHS status]
Lead Free Status Not applicable —
Current Distributor Rochester Electronics, LLC (authorized continuing source) —
Family — Classic EPLD
Device Type — EPLD (Erasable Programmable Logic Device)
Logic Delay (tPD) — 15 ns (pin-to-pin, -15 speed grade)
Maximum Counter Frequency — 100 MHz (per family datasheet)
Pipelined Data Rate — Up to 100 MHz
Technology — CMOS
Architecture — PAL-type, sum-of-products AND/OR array
TTL Emulation — 100% TTL compatible
Kiraan Pin — 24 pins
Development Tool — Altera MAX+PLUS II
Logic Test Circuitry — On-board for AC/DC verification

Laporan Datasheet & Sumber

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