EP910DC-40 vs EP910DC-30 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910DC-40 disebabkan oleh Altera dan EP910DC-30 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910DC-40 | EP910DC-30 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | PAL-type AND-OR sum-of-products, CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 36 |
| Bidirectional I/O Pins | 24 | — |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | — |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| Tegangan Pemberi Arus | 5 V (typical for Classic EPLD family) | 5 V |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| Kemasan | DIP-40 (ceramic, through-hole) | DIP-40 (through-hole, 600 mil) |
| Jenis Pemasangan | Through-Hole | Through-Hole |
| Status RoHS | [DATA_NEEDED: rohs_status] | — |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | UV-Erasable / OTP |
| Family | — | Classic EPLD (EP910 series) |
| Gate Count | — | 900 usable gates |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Process Technology | — | CMOS |
| Suhu Operasi | — | 0C to +70C (commercial) |