EP910IDC-15 vs EP910DC-15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910IDC-15 disebabkan oleh Altera dan EP910DC-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910IDC-15 | EP910DC-15 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Manufacturer | Altera (now Intel PSG) | — |
| Family | Classic EPLD | Altera Classic EPLD |
| Equivalent Gates | 450 | — |
| Macrocells | 24 | 24 |
| Flip-Flops | 48 | 10 |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Frequency (fCNT) | 66.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (typical) |
| Kemasan | 40-pin CDIP (Ceramic DIP, through-hole) | 24-pin ceramic DIP (DC) |
| Terminal Count | 40 | — |
| Terminal Form | Through-Hole | — |
| Temperature Grade | Commercial (0C to +70C) | — |
| Programmable Security Bit | Yes | — |
| On-board Test Circuitry | Yes | — |
| Logic Type | UV Erasable EPROM-based | — |
| I/O Pins | 24 | — |
| Dedicated Inputs | 10 | 12 |
| Programming Technology | EPROM (UV-erasable) | — |
| Status RoHS | non_compliant (ceramic DIP contains lead) | [DATA_NEEDED: not explicitly stated in verified data] |
| Device Density | — | 900 usable gates |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Bidirectional I/O Pins | — | 12 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Speed Grade | — | 15 |
| Suhu Operasi | — | 0C to +70C (commercial) |
| Technology | — | CMOS EPROM, UV-erasable |
| Jenis Pemasangan | — | Through-Hole |
| Aras MSL | — | [DATA_NEEDED: MSL level] |