EP910IDC-15 vs EP910DC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910IDC-15 sa pamamagitan ng Altera at EP910DC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910IDC-15 | EP910DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Manufacturer | Altera (now Intel PSG) | — |
| Family | Classic EPLD | Altera Classic EPLD |
| Equivalent Gates | 450 | — |
| Macrocells | 24 | 24 |
| Flip-Flops | 48 | 10 |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Frequency (fCNT) | 66.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (typical) |
| Packhaging | 40-pin CDIP (Ceramic DIP, through-hole) | 24-pin ceramic DIP (DC) |
| Terminal Count | 40 | — |
| Terminal Form | Through-Hole | — |
| Temperature Grade | Commercial (0C to +70C) | — |
| Programmable Security Bit | Yes | — |
| On-board Test Circuitry | Yes | — |
| Logic Type | UV Erasable EPROM-based | — |
| I/O Pins | 24 | — |
| Dedicated Inputs | 10 | 12 |
| Programming Technology | EPROM (UV-erasable) | — |
| Tindminan RoHS | non_compliant (ceramic DIP contains lead) | [DATA_NEEDED: not explicitly stated in verified data] |
| Device Density | — | 900 usable gates |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Bidirectional I/O Pins | — | 12 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Speed Grade | — | 15 |
| Temperature na Operasyon | — | 0C to +70C (commercial) |
| Technology | — | CMOS EPROM, UV-erasable |
| Uri ng Pagpapasok | — | Through-Hole |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |