EP910JM-40 vs EP910ILC-50 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910JM-40 disebabkan oleh Altera dan EP910ILC-50 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910JM-40 | EP910ILC-50 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Series | EP910 | — |
| Logic Type | EPLD (UV-Erasable PAL-type) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Product Terms | 240 | — |
| External Clock Inputs | 2 | — |
| Propagation Delay (tPD) | 40 ns | — |
| Process Technology | CMOS | — |
| Kemasan | JLCC-28 (windowed ceramic, J-lead) | PLCC-44 (J-lead) |
| Jenis Pemasangan | Surface Mount | Surface Mount (socket-compatible) |
| Status RoHS | [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] | [DATA_NEEDED: RoHS compliance status] |
| Programming Method | UV erase + EPROM programmer | — |
| Suhu Operasi | 0C to +70C (commercial) [DATA_NEEDED: confirm grade] | 0C to +70C (commercial) |
| Family | — | Altera Classic EPLD |
| Usable Gates | — | 900 (typical) |
| Maximum Frequency | — | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | — | 50 ns |
| Supply Voltage (VCC) | — | 5 V (typical) |
| User I/O Pins | — | 24 |
| Dedicated Input Pins | — | 12 |
| Technology | — | CMOS EPROM, UV-erasable |
| Programming Cycles | — | 100 (minimum) |
| Boundary Scan | — | IEEE 1149.1 JTAG (selected speed grades) |