EP910LI-12 vs EP910LI-50 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910LI-12 disebabkan oleh Altera dan EP910LI-50 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910LI-12 | EP910LI-50 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 450 |
| Propagation Delay (tPD) | 12 ns | 50 ns |
| Maximum Frequency (fMAX) | 76.9 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V typical) | 5 V +/- 10% |
| I/O Pins | 24 | [DATA_NEEDED: I/O pin count] |
| Inputs (with input registers) | 36 | — |
| Kemasan | 28-PLCC (windowed ceramic, J-Lead) | — |
| Suhu Operasi | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Process Technology | 1.0-micron CMOS EPROM | — |
| Power Dissipation (typical) | 200 mW at 5 V | — |
| Programming Method | UV-erasable via windowed package | EPROM programmer (UV-erasable window) |
| Logic Compatibility | TTL-compatible I/O | — |
| Status RoHS | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS status] |
| Family | — | Altera Classic EPLD |
| Package Type | — | CERDIP-40 (L) |
| Package Pin Count | — | 40 |
| Technology | — | CMOS, UV-erasable EPROM |
| Logic Blocks | — | Classic AND/OR array architecture |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Speed Grade Suffix | — | -50 (50 ns tPD) |