EP910PC-0 vs EP910PC-30 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910PC-0 disebabkan oleh Altera dan EP910PC-30 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910PC-0 | EP910PC-30 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EPLD | Altera Classic EPLD |
| Usable Gates | 900 gates | ~450 |
| Macrocells | 24 | 24 |
| Logic Blocks | 6 (4 macrocells each) | — |
| Dedicated Inputs | 10 | — |
| I/O Pins | 24 | 12 bidirectional |
| Kemasan | PDIP-40 (Plastic DIP, 40-pin) | PDIP-40 (plastic DIP, 0.6 inch) |
| Speed Grade | -0 (slowest) | — |
| Tegangan Pemberi Arus | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| Logic Compatibility | 100% TTL emulation | — |
| Suhu Operasi | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Method | UV-erasable / OTP | — |
| Jenis Pemasangan | Through-Hole (DIP) | Through-hole DIP |
| Pin-to-Pin Propagation Delay (tPD) | — | 30 ns |
| Maximum Counter Frequency (fCNT) | — | 33.3 MHz |
| Supply Voltage (VCC) | — | 5 V ±10% |
| Logic Inputs | — | 36 dedicated |
| Logic Array Blocks (LABs) | — | 4 |
| Programming Technology | — | UV-erasable EPROM cell |
| TTL Emulation | — | 100% TTL-compatible |
| Power Dissipation | — | [DATA_NEEDED: power dissipation mW] |
| Status RoHS | — | Non-compliant (contains lead, PDIP package) |