EP910PC-25 vs EP910IPC-15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910PC-25 disebabkan oleh Altera dan EP910IPC-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910PC-25 | EP910IPC-15 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Product Family | Classic EPLD | — |
| Usable Gates | 900 | — |
| Integration Gates (typical) | 4800 | — |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V +/- 10% | 4.75 V to 5.25 V |
| Technology | CMOS EPROM | — |
| Kemasan | PDIP-24 (Plastic DIP) | PDIP-40 (Plastic DIP, 40-pin) |
| Kiraan Pin | 24 | 40 |
| Dedicated Inputs | 10 | 12 |
| Dedicated I/O Pins | 12 | — |
| TTL Compatibility | 100% TTL emulation | — |
| Suhu Operasi | 0C to +70C (commercial) | 0C to +70C (commercial, IPC suffix) |
| Erasure Method | Not erasable in plastic package (windowless) | — |
| Device Family | — | Altera Classic EPLD (EP910 series) |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type, CMOS |
| I/O Pins | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Propagation Delay (tPD) | — | 15 ns |
| Jenis Pemasangan | — | Through-Hole |
| Process Technology | — | CMOS |
| Programming Method | — | JEDEC fuse map via Altera EPLD programmer |
| Status RoHS | — | [DATA_NEEDED: rohs status not confirmed in verified data] |