EP910PI-12T vs EP910PI-25 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910PI-12T disebabkan oleh Altera dan EP910PI-25 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910PI-12T | EP910PI-25 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 12 ns | — |
| Maximum Operating Frequency | 76.9 MHz | — |
| Logic Gates | [DATA_NEEDED: logic gate count] | — |
| Supply Voltage (VCC) | 5 V (4.75 V min, 5.25 V max) | 5 V nominal |
| I/O Pins | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| External Clock Inputs | 2 | — |
| Outputs | 24 | — |
| Terminals / Pin Count | 44 (PDIP-40 package pinout with NC pins) | — |
| Kemasan | 40-pin PDIP (Plastic DIP) | PDIP-40 (Plastic DIP) |
| Process Technology | CMOS | 5 V CMOS (EPROM-based) |
| Suhu Operasi | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programmable Technology | UV-erasable EPROM | — |
| Programming Interface | JEDEC-standard | — |
| Status RoHS | Non-compliant (legacy PDIP package, contains lead) | Non-compliant (PDIP package) |
| Status Lingkungan Hidup | NRND / EOL (mature legacy product) | — |
| Device | — | EP910 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Clock Frequency (fMAX) | — | 40 MHz |
| Kiraan Pin | — | 40 |
| Jenis Pemasangan | — | Through-Hole |
| Programmability | — | UV-erasable (windowed) / one-time-programmable |