EP910PI-40 vs EP910PI-25 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910PI-40 disebabkan oleh Altera dan EP910PI-25 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EP910PI-40 - 24-Macrocell Classic EPLD, 43ns, PDIP-40 | Altera
EP910PI-40 ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EP910PI-40 | EP910PI-25 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Obsolete |
| Device Family | Classic EPLD | — |
| Part Number | EP910PI-40 | — |
| Architecture | PAL-type macrocell, CMOS, UV-erasable | — |
| Number of Macrocells | 24 | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Lines | 24 | — |
| External Clock Inputs | 2 | — |
| Frekuensi Klock Maksimum | 25 MHz | — |
| Propagation Delay (tPD) | 43 ns | — |
| Speed Grade | -40 (43 ns) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V nominal |
| Kemasan | PDIP-40 (Plastic DIP, 40-pin) | PDIP-40 (Plastic DIP) |
| Suhu Operasi | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Jenis Pemasangan | Through-Hole | Through-Hole |
| Process Technology | CMOS (UV-erasable) | 5 V CMOS (EPROM-based) |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | Non-compliant (PDIP package) |
| Programming Method | UV-erase + Altera programmer (legacy) | — |
| Programmable Polarity | Yes (user-configurable output) | — |
| Output Enable Control | Yes (per-pin three-state) | — |
| Family | — | Altera Classic EPLD |
| Device | — | EP910 |
| Macrocells | — | 24 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Clock Frequency (fMAX) | — | 40 MHz |
| Kiraan Pin | — | 40 |
| Programmability | — | UV-erasable (windowed) / one-time-programmable |