EP910PI-40 vs EP910PI-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-40 sa pamamagitan ng Altera at EP910PI-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-40 | EP910PI-25 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Device Family | Classic EPLD | — |
| Part Number | EP910PI-40 | — |
| Architecture | PAL-type macrocell, CMOS, UV-erasable | — |
| Number of Macrocells | 24 | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Lines | 24 | — |
| External Clock Inputs | 2 | — |
| Maksimum na Taktiko ng Oras | 25 MHz | — |
| Propagation Delay (tPD) | 43 ns | — |
| Speed Grade | -40 (43 ns) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V nominal |
| Packhaging | PDIP-40 (Plastic DIP, 40-pin) | PDIP-40 (Plastic DIP) |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Uri ng Pagpapasok | Through-Hole | Through-Hole |
| Process Technology | CMOS (UV-erasable) | 5 V CMOS (EPROM-based) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Non-compliant (PDIP package) |
| Programming Method | UV-erase + Altera programmer (legacy) | — |
| Programmable Polarity | Yes (user-configurable output) | — |
| Output Enable Control | Yes (per-pin three-state) | — |
| Family | — | Altera Classic EPLD |
| Device | — | EP910 |
| Macrocells | — | 24 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Clock Frequency (fMAX) | — | 40 MHz |
| Bilang ng Pin | — | 40 |
| Programmability | — | UV-erasable (windowed) / one-time-programmable |