EPC144LC-20 vs EPC1441LI20 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPC144LC-20 disebabkan oleh Altera dan EPC1441LI20 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPC144LC-20 | EPC1441LI20 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Jenis Ingatan | OTP EPROM (One-Time Programmable) | OTP Configuration PROM (PROM) |
| Saiz Ingatan | 440,800 bits (440 kb) | — |
| Configuration Interface | Altera serial daisy-chain | Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS) |
| Access Time (Speed Grade) | 20 ns | — |
| Supply Voltage (VCC) | [DATA_NEEDED: VCC min/max] | — |
| Supply Voltage (VPP) | [DATA_NEEDED: VPP programming voltage] | — |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (industrial) |
| Package Type | 20-pin PLCC (J-lead) | — |
| Package Dimensions | 9 x 9 mm | — |
| Jenis Pemasangan | Surface Mount | — |
| Compatible FPGA Families | FLEX 10K, FLEX 8000, ACEX 1K | — |
| Programming Method | Altera Logic Programmer / JTAG | One-Time-Programmable via Altera programming hardware |
| Process Technology | CMOS | — |
| Aras MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Daisy-Chain Support | Yes (multiple PROMs cascadable) | — |
| Manufacturer | Altera (now Intel FPGA) | — |
| Density | — | 441 kbits (440,800 bits) |
| Number of Words | — | 440,800 |
| Bits per Word | — | 1 bit |
| Supported FPGA Families | — | ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury |
| Tegangan Pemberi Arus | — | 3.3 V |
| Kemasan | — | 20-pin PLCC (J-lead, 9x9 mm) |
| Pin Pitch | — | 1.27 mm |
| Configuration Time | — | Depends on FPGA bitstream length and DCLK frequency |