EPC1LC20-WCEC52 vs EPC1LC20-W Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPC1LC20-WCEC52 disebabkan oleh Altera dan EPC1LC20-W disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPC1LC20-WCEC52 | EPC1LC20-W |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Jenis Ingatan | OTP Configuration PROM (Anti-fuse) | OTP (One-Time Programmable) Configuration PROM |
| Saiz Ingatan | 1 Mbit (1,048,576 bits) | 1 Mbit |
| Organisasi | 212,942 x 1 bit | — |
| Antaramuka | Serial (Altera FPP/PS configuration protocol) | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| Configuration Clock (DCLK) | 8 MHz maximum | 8 MHz maximum |
| Supply Voltage (VCC) | 3.3 V | — |
| I/O Voltage Tolerance | 5.0 V (FPGA interface) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Programmability | One-Time Programmable (OTP) | — |
| Suhu Operasi | -40C to +85C (industrial) | — |
| Kemasan | 20-pin PLCC (J-lead, through-hole, 9x9 mm) | 20-PLCC J-lead (9x9 mm) |
| Package Mounting | Through-hole (also accepts PLCC socket) | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | Compliant (Pb-free -W finish) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Compatible FPGA Families | Cyclone, Stratix, APEX, ACEX, MAX series | — |
| Programming Interface | JTAG (IEEE Std 1149.1) ISP | — |
| Kiraan Pin | 20 | — |
| Status Lingkungan Hidup | Obsolete (recommended replacement: EPCQ family or newer serial config devices) | — |
| Tegangan Pemberi Arus | — | 3.3 V and 5.0 V |
| In-System Programming | — | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | — | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | — | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | — | Yes - stores compressed Altera FPGA bitstreams |
| Gambaran Suhu Operasi | — | [DATA_NEEDED: operating temperature range] |
| Programming Cycles | — | 1 (OTP) |
| Target FPGA Families | — | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |
| Jenis Pemasangan | — | Surface Mount (PLCC socket or direct solder) |