EPF8636ARC208-4 vs EPF8820ARC208-3 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPF8636ARC208-4 disebabkan oleh Altera dan EPF8820ARC208-3 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Intel
EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera
EPF8820ARC208-3 ObsoletePengandingan Spesifikasi
| Parametr | EPF8636ARC208-4 | EPF8820ARC208-3 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Product Family | FLEX 8000 | — |
| Device Series | EPF8636A | — |
| Usable Gates | 6,000 | 8,000 |
| Logic Elements | 136 | — |
| Flip-Flops (Registers) | 504 | — |
| Maximum User I/O | 218 | — |
| Embedded RAM Blocks | 8 x 256 x 8 bits | — |
| Logic Block Type | 4-input LUT with fast-carry chain | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| I/O Voltage Tolerance | 3.3 V or 5 V | — |
| Speed Grade | -4 | — |
| Suhu Operasi | -40 C to +105 C | — |
| Kemasan | 208-RQFP (28x28 mm) with exposed pad | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Process Technology | 5 V CMOS, 0.42 um | 0.42 µm CMOS |
| Configuration Method | Serial configuration EEPROM (in-system) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Status RoHS | Non-compliant (legacy 5 V family) | [DATA_NEEDED: RoHS status] |
| Series | — | FLEX 8000 |
| Family | — | FLEX 8000 (EPF8820) |
| Logic Cells / Elements | — | 672 |
| Registers | — | 152 |
| Maximum Operating Frequency | — | 125 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Configuration Memory | — | SRAM (volatile) |
| Kemasan / Case | — | 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm) |
| Supplier Device Package | — | 208-RQFP (28x28) |
| Packaging | — | Tray |
| Gambaran Suhu Operasi | — | [DATA_NEEDED: operating temperature range] |
| In-Circuit Reconfigurability (ICR) | — | Yes (via external configuration devices) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| I/O Tolerance | — | 3.3 V / 5 V |
| Clock Networks | — | 4 dedicated low-skew global clocks |
| Lead-Free / Finish | — | [DATA_NEEDED: lead-free finish] |