EPM240F100C5N vs EPM240GM100C5N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM240F100C5N disebabkan oleh Intel dan EPM240GM100C5N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM240GM100C5N - 192-Cell MAX II G CPLD, 4.7ns, 100-MBGA | Intel / Altera
EPM240GM100C5N ✓ AktifPengandingan Spesifikasi
| Parametr | EPM240F100C5N | EPM240GM100C5N |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | Aktif |
| Device Family | MAX II | — |
| Logic Elements (LEs) | 240 | — |
| Macrocells | 192 | — |
| User I/O Pins (maximum) | 80 | — |
| Pin-to-Pin Logic Delay (tPD) | 4.7 ns | — |
| Maximum Operating Frequency | [DATA_NEEDED: fmax per datasheet] | — |
| Global Clock Networks | [DATA_NEEDED: count] | — |
| Kemasan | 100-ball FineLine BGA (FBGA-100) | 100-MBGA (Micro FineLine BGA), 6 x 6 mm |
| Gambaran Suhu Operasi | 0C to +85C (commercial) | — |
| Supply Voltage Core (VCCINT) | 3.3 V | — |
| I/O Bank Voltage (VCCIO) | 1.5V / 1.8V / 2.5V / 3.3V (MultiVolt) | — |
| Configuration Memory | Non-volatile flash (instant-on) | Non-volatile Flash |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Programming Interface | JTAG / ByteBlasterMV | JTAG (IEEE 1149.1) - ISP |
| Jenis Pemasangan | Surface Mount (BGA) | Surface Mount (BGA) |
| Status RoHS | Compliant | — |
| Family | — | MAX II G |
| Logic Elements | — | 240 (192 macrocells) |
| User I/Os | — | 80 |
| Pin-to-Pin Delay (tPD) | — | 4.7 ns |
| Ball Pitch | — | 0.5 mm |
| Supply Voltage - Core | — | 3.3 V |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multiVolt) |
| Suhu Operasi | — | -40 C to +125 C |
| Lead Free / RoHS | — | Yes / Compliant |
| Aras MSL | — | 3 |
| Process Technology | — | CMOS, Flash-based |