EPM240GF100I5N vs EPM240M100C4N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM240GF100I5N disebabkan oleh Altera dan EPM240M100C4N disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM240GF100I5N | EPM240M100C4N |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | Aktif |
| Series | MAX II | MAX II |
| Logic Elements / Blocks | 240 LE | — |
| Number of Macrocells | 192 | — |
| Maximum User I/O | 80 | — |
| Propagation Delay (tpd, max) | 4.7 ns | — |
| Programmable Type | In-System Programmable (ISP) | — |
| Non-Volatile Memory | On-chip flash configuration | — |
| Internal Supply Voltage | 1.71 V to 1.89 V (regulated on-chip) | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Kemasan | 100-ball FBGA (FineLine BGA), 11 mm x 11 mm, 1.0 mm pitch | 100-pin Micro FineLine BGA (MBGA), 6 x 6 mm, 0.5 mm pitch |
| Operating Temperature (TJ) | -40 C to +100 C | — |
| Jenis Pemasangan | Surface Mount | Surface Mount (BGA) |
| JTAG Support | IEEE 1149.1 / IEEE 1532 compliant | — |
| Lead-Free / RoHS | Yes (lead-free, RoHS compliant) | — |
| Logic Family | CMOS | CMOS |
| Vertical Migration Family | EPM240 / EPM570 / EPM1270 / EPM2210 in same-package footprint | — |
| Device Family | — | EPM240 |
| Macro Cells | — | 192 |
| User I/Os | — | 80 |
| Propagation Delay (tPD) Max | — | 4.7 ns |
| Internal Operating Frequency | — | 247.5 MHz |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| User Flash Memory | — | 8 Kbit |
| Programmability | — | In-System Programmable via JTAG (IEEE 1149.1) |
| Configuration Memory | — | Non-volatile on-chip flash (instant-on) |
| Suhu Operasi | — | -40 C to +125 C (industrial) |
| Status RoHS | — | Lead Free (per DigiChip spec sheet) |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells per LAB) |
| MultiTrack Interconnect | — | Yes |
| Hot Socketing | — | Yes |