EPM3064ATC100-7 vs EPM3064ATC100-4 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3064ATC100-7 disebabkan oleh Altera dan EPM3064ATC100-4 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM3064ATC100-7 EPM3064ATC100-4
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Family MAX 3000A MAX 3000A
Usable Gates 1,250 1,250 (range 600 to 10,000 across family)
Macrocells 64 —
Logic Array Blocks (LABs) 2 2
Maximum User I/Os 66 (in 100-pin TQFP) —
Pin-to-Pin Propagation Delay (tPD) 7.5 ns (-7 speed grade) —
Maximum Internal Counter Frequency 135.1 MHz —
Supply Voltage - VCCINT (Core) 3.3 V —
Supply Voltage - VCCIO (I/O) 2.5 V or 3.3 V (5.0 V tolerant inputs) —
Technology CMOS EEPROM —
Kemasan 100-pin TQFP 100-pin TQFP
Jenis Pemasangan Surface Mount Surface Mount
Suhu Operasi 0C to +70C (commercial) 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option]
In-System Programming (ISP) Yes, via IEEE 1149.1 JTAG —
PCI Compliance PCI Local Bus Specification Revision 2.2 —
JTAG Boundary Scan Yes —
Lead Free / RoHS Compliant (modern shipments) —
Device Type — CPLD (EEPROM-based)
Macro Cells — 64
Maximum User I/O Pins — 34
Pin-to-Pin Delay (tPD) — 4.5 ns
Counter Frequency (fCNT) — 227.3 MHz
Internal Performance — 222.2 MHz
Supply Voltage VCCINT — 3.3 V
I/O Voltage (MultiVolt) — 2.5 V / 3.3 V / 5.0 V
In-System Programming — Yes (IEEE 1149.1 JTAG)
Process Technology — CMOS EEPROM
Status RoHS — unknown
Architecture — 5-level Altera MAX

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