EPM3064ATC100-7 vs EPM3064ATC100-4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC100-7 sa pamamagitan ng Altera at EPM3064ATC100-4 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3064ATC100-7 - MAX 3000A 64-Macrocell CPLD, 7.5ns, 100-TQFP | Altera
EPM3064ATC100-7 ObsoletePagsanggunian na paghahambing
| Parametro | EPM3064ATC100-7 | EPM3064ATC100-4 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 3000A | MAX 3000A |
| Usable Gates | 1,250 | 1,250 (range 600 to 10,000 across family) |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 2 | 2 |
| Maximum User I/Os | 66 (in 100-pin TQFP) | — |
| Pin-to-Pin Propagation Delay (tPD) | 7.5 ns (-7 speed grade) | — |
| Maximum Internal Counter Frequency | 135.1 MHz | — |
| Supply Voltage - VCCINT (Core) | 3.3 V | — |
| Supply Voltage - VCCIO (I/O) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| Technology | CMOS EEPROM | — |
| Packhaging | 100-pin TQFP | 100-pin TQFP |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option] |
| In-System Programming (ISP) | Yes, via IEEE 1149.1 JTAG | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | — |
| JTAG Boundary Scan | Yes | — |
| Lead Free / RoHS | Compliant (modern shipments) | — |
| Device Type | — | CPLD (EEPROM-based) |
| Macro Cells | — | 64 |
| Maximum User I/O Pins | — | 34 |
| Pin-to-Pin Delay (tPD) | — | 4.5 ns |
| Counter Frequency (fCNT) | — | 227.3 MHz |
| Internal Performance | — | 222.2 MHz |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Voltage (MultiVolt) | — | 2.5 V / 3.3 V / 5.0 V |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Process Technology | — | CMOS EEPROM |
| Tindminan RoHS | — | unknown |
| Architecture | — | 5-level Altera MAX |