EPM3128ATC100-10 vs EPM3128ATI100-10 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3128ATC100-10 disebabkan oleh Altera dan EPM3128ATI100-10 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM3128ATC100-10 EPM3128ATI100-10
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Aktif
Device Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 128 —
User I/Os 80 80
Usable Gates 2500 2,500
Propagation Delay (tPD) 10 ns —
Counter Frequency 227.3 MHz —
Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Voltage Tolerance 5.0 V / 3.3 V / 2.5 V (MultiVolt) —
Kemasan 100-pin TQFP TQFP-100 (1.0 mm pitch, 14x14 mm)
Jenis Pemasangan Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile) —
In-System Programming IEEE Std. 1532 compliant (JTAG) —
PCI Compliance PCI Local Bus Specification Rev 2.2 (selected speed grades) —
Logic Family CMOS —
Suhu Operasi 0 C to 70 C (commercial) -40 °C to +85 °C (industrial)
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free]
Family — MAX 3000A
Macro Cells — 128
Logic Elements / LABs — [DATA_NEEDED: LAB count]
Pin-to-Pin Delay (tPD) — 10 ns
Counter Frequency (fCNT) — up to 227.3 MHz
MultiVolt I/O Levels — 5.0 V / 3.3 V / 2.5 V compatible
Programmability — EEPROM, 3.3 V in-system (JTAG)
Process Technology — CMOS EEPROM
Open-Drain Output Option — Yes (per I/O pin)
Boundary-Scan (JTAG) — IEEE 1149.1 compliant

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga