EPM3128ATC100-10 vs EPM3128ATI100-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128ATC100-10 sa pamamagitan ng Altera at EPM3128ATI100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3128ATC100-10 - MAX 3000A 128-Macrocell CPLD, 10ns TQFP-100 | Intel / Altera
EPM3128ATC100-10 NrndAltera
EPM3128ATI100-10 - 128-Macro MAX 3000A CPLD, 10ns TQFP-100 | Altera
EPM3128ATI100-10 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM3128ATC100-10 | EPM3128ATI100-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Aktibo |
| Device Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | — |
| User I/Os | 80 | 80 |
| Usable Gates | 2500 | 2,500 |
| Propagation Delay (tPD) | 10 ns | — |
| Counter Frequency | 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Voltage Tolerance | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Packhaging | 100-pin TQFP | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programming | IEEE Std. 1532 compliant (JTAG) | — |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (selected speed grades) | — |
| Logic Family | CMOS | — |
| Temperature na Operasyon | 0 C to 70 C (commercial) | -40 °C to +85 °C (industrial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free] |
| Family | — | MAX 3000A |
| Macro Cells | — | 128 |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| MultiVolt I/O Levels | — | 5.0 V / 3.3 V / 2.5 V compatible |
| Programmability | — | EEPROM, 3.3 V in-system (JTAG) |
| Process Technology | — | CMOS EEPROM |
| Open-Drain Output Option | — | Yes (per I/O pin) |
| Boundary-Scan (JTAG) | — | IEEE 1149.1 compliant |