EPM3128ATC100-10N vs EPM3128ATC100-10NS Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3128ATC100-10N disebabkan oleh Altera dan EPM3128ATC100-10NS disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N NrndPengandingan Spesifikasi
| Parametr | EPM3128ATC100-10N | EPM3128ATC100-10NS |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | 128 |
| Usable Gates | 2500 | — |
| Number of I/O | 80 | — |
| Logic Elements / Blocks | 8 LABs (16 macrocells each) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency (fMAX) | 98 MHz | — |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Bank Voltage VCCIO | 3.3 V or 2.5 V (selectable) | — |
| Configuration Memory | CMOS EEPROM (non-volatile, instant-on) | EEPROM (non-volatile) |
| In-System Programming | IEEE Std. 1532-compliant ISP via JTAG | — |
| Kemasan | 100-pin TQFP (14 x 14 x 1.0 mm) | TQFP-100 |
| Suhu Operasi | 0 °C to +70 °C (commercial) | [DATA_NEEDED: operating temperature range] |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Status RoHS | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | Yes | [DATA_NEEDED: lead-free status] |
| Aras MSL | 3 (per JEDEC J-STD-020) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| User I/Os | — | 80 |
| Kiraan Pin | — | 100 |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| Supply Voltage - I/O (VCCIO) | — | 3.3 V or 2.5 V (5.0 V-tolerant inputs) |
| Logic-Level Compatibility | — | 5.0 V, 3.3 V, 2.5 V |
| Programmability | — | In-system (ISP), IEEE Std. 1532 |
| Boundary Scan | — | IEEE 1149.1 JTAG |