EPM3512AFC256-21 vs EPM3512AFC256-18 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3512AFC256-21 disebabkan oleh Altera dan EPM3512AFC256-18 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM3512AFC256-21 EPM3512AFC256-18
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Device Family MAX 3000A —
Logic Elements / Macrocells 512 macrocells —
Usable Gates 10,000 —
Logic Array Blocks (LABs) 16 16
Maximum Operating Frequency 87 MHz —
Kemasan FBGA-256 (FineLine BGA) 256-ball FineLine BGA (FCBGA)
Suhu Operasi -40C to +85C (industrial) [DATA_NEEDED: industrial/commercial grade]
Supply Voltage - Core (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) —
Programmable Pins (max) [DATA_NEEDED: maximum user I/O pin count] —
Programming Interface JTAG / IEEE Std. 1532 ISP —
Jenis Ingatan Non-volatile EPROM/EEPROM cell array —
Jenis Pemasangan Surface Mount (BGA) Surface Mount
Status RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: not specified in retrieved data]
Lead-Free [DATA_NEEDED: lead-free status] —
Family — MAX 3000A
Macrocells — 512
Maximum User I/O Pins — 212
Pin-to-Pin Delay (tPD1) — 18 ns
Global Clock Networks — 4
VCCINT (Core Supply) — 3.0 V to 3.6 V (3.3 V typical)
VCCIO (I/O Supply) — 2.5 V or 3.3 V (MultiVolt)
Programming Technology — EEPROM (non-volatile)
In-System Programming — IEEE Std. 1532 / JTAG (IEEE Std. 1149.1)
Ball Pitch — 1.0 mm

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