EPM3512AFC256-7 vs EPM3512AFC256C Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3512AFC256-7 disebabkan oleh Intel dan EPM3512AFC256C disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Intel
EPM3512AFC256-7 - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel
EPM3512AFC256-7 ⚠ Bahagian terakhir untuk beliIntel
EPM3512AFC256C - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256C ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPM3512AFC256-7 | EPM3512AFC256C |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Masa Terakhir Dibeli |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| User I/O Pins | 212 | — |
| Usable Gates | 10,000 | — |
| Pin-to-Pin Logic Delay | 7.5 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.0 V to 3.6 V (3.3 V typ.) | — |
| I/O Voltage (VCCIO) | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Kemasan | 256-ball FineLine BGA (FBGA-256) | 256-ball FineLine BGA (FC) |
| Programming | EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant) | In-system programmable via JTAG |
| Suhu Operasi | [DATA_NEEDED: operating temperature grade] | 0C to +70C (Commercial) |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Configuration Memory | Non-volatile EEPROM | — |
| Maximum User I/Os | — | 208 |
| Dedicated Input Pins | — | 12 |
| Speed Grade | — | C (per datasheet ordering code) |
| Configuration Technology | — | EEPROM (non-volatile, instant-on) |
| Core Voltage | — | 3.3 V |
| I/O Standards Supported | — | MultiVolt: 5.0 V, 3.3 V, 2.5 V |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| PCI Compliance | — | PCI SIG Local Bus Specification Revision 2.2 |