EPM3512AQC208-10-10N vs EPM3512AQC208-10S Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3512AQC208-10-10N disebabkan oleh Altera dan EPM3512AQC208-10S disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM3512AQC208-10-10N EPM3512AQC208-10S
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 3000A MAX 3000A
Macrocells 512 512
Usable Gates 10,000 1750
User I/Os 172 208
Logic Elements / LABs 16 Logic Array Blocks —
Propagation Delay (tPD) 10 ns (-10 speed grade) —
Maximum Frequency (fCNT) 87 MHz —
Supply Voltage - Core (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V —
Process Technology CMOS EEPROM EEPROM-based CMOS
In-System Programmability Yes, IEEE Std. 1532 compliant —
Boundary-Scan (JTAG) Yes, IEEE 1149.1 Yes (1149.1 compliant)
PCI-SIG Compliance PCI Local Bus Specification Rev 2.2 (at -10 speed grade) —
Suhu Operasi 0 °C to +70 °C (commercial) 0C to +70C (commercial)
Kemasan 208-pin PQFP (Plastic Quad Flat Pack) 208-pin FineLine BGA-256
Jenis Pemasangan Surface Mount —
Lead-Free / RoHS [DATA_NEEDED: RoHS status] —
Device Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — 32 (16 macrocells each)
Speed Grade — -10 (tPD1 = 7.5 ns)
Propagation Delay (tPD1) — 7.5 ns (pin-to-pin)
Supply Voltage - VCCINT (internal) — 3.3 V
Supply Voltage - VCCIO (I/O) — 2.5 V, 3.3 V, or 5.0 V (MultiVolt)
Programming Technology — CMOS EEPROM
In-System Programmability (ISP) — Yes (IEEE Std. 1149.1 JTAG)
PCI Compliance — Yes (PCI Local Bus Specification Rev 2.2)
Program/Erase Endurance — 100 cycles minimum
Logic Family — CMOS
Status RoHS — [DATA_NEEDED: rohs_status]

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