EPM3512AQC208-7N vs EPM3512AQC208-10NS Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3512AQC208-7N disebabkan oleh Altera dan EPM3512AQC208-10NS disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EPM3512AQC208-7N EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EPM3512AQC208-7N EPM3512AQC208-10NS
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Masa Terakhir Dibeli Aktif
Family MAX 3000A MAX 3000A
Logic Capacity 512 macrocells, 10,000 usable gates —
Logic Array Blocks (LABs) 32 12
Macrocells per LAB 16 —
User I/Os 172 172
Propagation Delay (tPD) 7.5 ns —
Maximum Frequency (fCNT) 116.3 MHz —
Supply Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) —
I/O Bank Count 4 (MultiVolt) —
Supported I/O Standards 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS —
Process Technology 0.30 µm CMOS EEPROM —
Configuration Non-volatile EEPROM, in-system programmable (ISP) Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532)
JTAG Interface IEEE 1149.1 BST + IEEE 1532 ISP —
Kemasan 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) 208-pin PQFP
Suhu Operasi 0 °C to +70 °C (commercial) 0C to +70C (commercial)
Status RoHS Compliant [DATA_NEEDED: rohs status]
Speed Grade -7 —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 512
Usable Gates — 10,000
Pin-to-Pin Delay (tPD) — 10 ns (speed grade -10)
Internal Counter Frequency — 227.3 MHz max
Propagation Delay — 7.5 ns (datasheet figure)
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (MultiVolt)
Logic Family — CMOS, EEPROM-based
ISP Standard — IEEE Std. 1532
Jenis Pemasangan — Surface Mount

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