EPM3512AQC208-7N vs EPM3512AQC208-10NS Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC208-7N sa pamamagitan ng Altera at EPM3512AQC208-10NS sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera
EPM3512AQC208-7N ⚠ Huling PagbiliAltera
EPM3512AQC208-10NS - MAX 3000A 512-Macro CPLD, 208-PQFP | Altera
EPM3512AQC208-10NS ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM3512AQC208-7N | EPM3512AQC208-10NS |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Family | MAX 3000A | MAX 3000A |
| Logic Capacity | 512 macrocells, 10,000 usable gates | — |
| Logic Array Blocks (LABs) | 32 | 12 |
| Macrocells per LAB | 16 | — |
| User I/Os | 172 | 172 |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Frequency (fCNT) | 116.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Bank Count | 4 (MultiVolt) | — |
| Supported I/O Standards | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Configuration | Non-volatile EEPROM, in-system programmable (ISP) | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) |
| JTAG Interface | IEEE 1149.1 BST + IEEE 1532 ISP | — |
| Packhaging | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) | 208-pin PQFP |
| Temperature na Operasyon | 0 °C to +70 °C (commercial) | 0C to +70C (commercial) |
| Tindminan RoHS | Compliant | [DATA_NEEDED: rohs status] |
| Speed Grade | -7 | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 512 |
| Usable Gates | — | 10,000 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (speed grade -10) |
| Internal Counter Frequency | — | 227.3 MHz max |
| Propagation Delay | — | 7.5 ns (datasheet figure) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Logic Family | — | CMOS, EEPROM-based |
| ISP Standard | — | IEEE Std. 1532 |
| Uri ng Pagpapasok | — | Surface Mount |